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PDF NB7HQ14M Data sheet ( Hoja de datos )
| Número de pieza | NB7HQ14M | |
| Descripción | 2.5V 7GHz / 10Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB7HQ14M
2.5V 7GHz / 10Gbps
Differential Input to 1.8V /
2.5V 1:4 CML Clock / Data
Fanout Buffer w/ Selectable
Input Equalizer
Multi−Level Inputs w/ Internal Termination
Description
The NB7HQ14M is a high performance differential 1:4 CML fanout
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 7 GHz or 10 Gb/s, respectively, the
NB7HQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal. Therefore, the serial data rate
is increased by reducing Inter−Symbol Interference (ISI) caused by
losses in copper interconnect or long cables. The EQualizer ENable
pin (EQEN) allows the IN/IN inputs to either flow through or bypass
the Equalizer section. Control of the Equalizer function is realized by
setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the
Equalizer. When EQEN is set High, the IN/IN inputs flow through the
Equalizer. The default state at start−up is LOW. As such, NB7HQ14M
is ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT pin. This feature allows the
NB7HQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The outputs have the flexibility of being powered by
either a 2.5 V or 1.8 V supply. The 1:4 fanout design was optimized
www.DatfaoSrhleoewt4Uou.ctopmut skew applications.
The NB7HQ14M is a member of the GigaComm™ family of high
performance clock products.
Features
• Input Data Rate > 10 Gb/s
• Input Clock Frequency > 7 GHz
• 150 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• < 15 ps Maximum Output Skew
• < 0.8 ps Maximum RMS Clock Jitter
• < 10 ps pp of Data Dependent Jitter
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical
• Selectable Input Equalization
• Operating Range: VCC = 2.375 V to 2.625 V, VCCO = 1.71 V to
2.625 V
• Internal Input Termination Resistors, 50 W
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7H
Q14M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
EQ
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
May, 2009 − Rev. 0
1
Publication Order Number:
NB7HQ14M/D
1 page  
NB7HQ14M
Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = 2.375 V to 2.625 V; VCCO = 1.71 V to 2.625 V; GND = 0 V;
TA = −40°C to 85°C (Note 5)
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY / CURRENT
VCC
VCCO
Power Supply Voltage
VCC = 2.5 V
2.375
2.5
2.625
V
VCCO = 2.5 V
2.375
2.5
2.625
VCCO = 1.8 V
1.71
1.8
1.89
ICC
ICCO
Power Supply Current for VCC (Inputs and Outputs Open)
Power Supply Current for VCCO (Inputs and Outputs Open)
95 135 mA
65 85
CML OUTPUTS (Note 6)
VOH Output HIGH Voltage
VCCO = 2.5 V
VCCO = 1.8 V
VOL Output LOW Voltage
VCCO = 2.5 V
VCCO = 1.8 V
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figure 5 & 7) (Note 7)
VCCO – 30
2470
1770
VCCO – 550
1950
1250
VCCO – 10
2490
1790
VCCO – 400
2100
1400
VCCO
2500
1800
VCCO – 300
2200
1500
mV
mV
VIH
VIL
Vth
VISE
VREFAC
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage Amplitude (VIH − VIL)
Vth + 100
GND
1100
200
VCC
Vth −100
VCC − 100
2800
mV
mV
mV
mV
VREFAC Output Reference Voltage @100 mA for capacitor− coupled inputs, only VCC – 1325 VCC – 1125
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 6 & 8) (Note 9)
VCC – 925
mV
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (VIHD − VILD)
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
1200
0
100
1050
VCC
VIHD − 100
1200
VCC − 50
mV
mV
mV
mV
IIH Input HIGH Current IN / IN, (VT Open)
IIL Input LOW Current IN / IN, (VT Open)
www.DataCSOheNeTt4RUO.LcoImNPUTS (EQEN)
−150
−150
150 uA
150 uA
VIH Input HIGH Voltage for Control Pins
VIL Input LOW Voltage for Control Pins
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
VCC x 0.65
GND
−150
−150
VCC
VCC x 0.35
150
150
V
V
mA
mA
RTIN
RTOUT
Internal Input Termination Resistor
Internal Output Termination Resistor
45 50 55 W
45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with VCC. Output parameters vary 1:1 with VCCO.
6. CML outputs loaded with 50 W to VCCO for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the crosspoint side of the differential input
signal.
http://onsemi.com
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