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NB7L1008M PDF даташит

Спецификация NB7L1008M изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «Multi-Level Inputs w/ Internal Termination».

Детали детали

Номер произв NB7L1008M
Описание Multi-Level Inputs w/ Internal Termination
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NB7L1008M Даташит, Описание, Даташиты
NB7L1008M
2.5V / 3.3V 1:8 CML Fanout
MultiLevel Inputs w/ Internal
Termination
Description
The NB7L1008M is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008M produces eight identical output copies
of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As
such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pin. This feature allows the NB7L1008M
to accept various logic standards, such as LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels. The VREFAC reference output can
be used to rebias capacitorcoupled differential or singleended input
signals. The 1:8 fanout design was optimized for low output skew
applications. The NB7L1008M is a member of the GigaComm
family of high performance clock products.
Features
Input Data Rate > 12 Gb/s Typical
Data Dependent Jitter < 20 ps
Maximum Input Clock Frequency > 8 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:8 CML Outputs, < 25 ps max
MultiLevel Inputs, accepts LVPECL, CML, LVDS
160 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
www.DataSDheiefft4eUre.ncotimal CML Outputs, 400 mV PeaktoPeak, Typical
Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output
QFN32 Package, 5 mm x 5 mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
MARKING
32 DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
1008M
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
SIMPLIFIED LOGIC DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
IN
VT 50W
50W
IN
VREFAC
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
© Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 0
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
1 Publication Order Number:
NB7L1008M/D









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NB7L1008M Даташит, Описание, Даташиты
NB7L1008M
Exposed Pad
(EP)
32 31 30 29 28 27 26 25
VCC 1
24 GND
GND 2
23 VCC
IN 3
22 Q3
VT 4
VREFAC 5
NB7L1008M
21 Q3
20 Q4
IN 6
19 Q4
GND 7
18 VCC
VCC 8
17
GND
9 10 11 12 13 14 15 16
Figure 1. 32Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
3, 6
IN, IN
LVPECL, CML, Noninverted / Inverted Differential Clock/Data Input. Note 1
LVDS Input
4 VT
Internal 50 W Termination Pin for IN and IN
2, 7 17,24
GND
Negative Supply Voltage, Note 2
1, 8, 9, 16, 18,
23, 25, 32
VCC
Positive Supply Voltage, Note 2
31, 30, 29, 28,
27, 26, 22, 21,
20, 19, 15, 14,
www.DataS13h,e1e2t4, U11.c,o1m0
Q0, Q0, Q1,
Q1, Q2, Q2,
Q3, Q3, Q4,
Q4, Q5, Q5,
Q6, Q6, Q7, Q7
CML
Noninverted / Inverted Differential Output. Note 1
5 VREFAC
Output Voltage Reference for CapacitorCoupled Inputs, only
EP
The Exposed Pad (EP) on the QFN24 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heatsinking conduit. The pad is electrically connected to GND and is
recommended to be electrically connected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN, then the device will be susceptible to selfoscillation. Qn/Qn outputs have internal 50 W source termination resistors.
2. All VCC and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
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NB7L1008M Даташит, Описание, Даташиты
NB7L1008M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 3) Indefinite Time of the Drypack
QFN32
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, refer to Application Note AND8003/D.
Value
> 2 kV
> 200 V
Level 1
UL 94 V0 @ 0.125 in
263
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1 Condition 2
Rating
Unit
VCC
VIN
VINPP
IIN
Iout
Positive Power Supply
Input Voltage
Differential Input Voltage |IN IN|
Input Current Through RT (50 W Resistor)
Output Current
GND = 0 V
GND = 0 V
Continuous
Surge
4.0
0.5 to VCC
1.89
$40
34
40
V
V
V
mA
mA
IVFREFAC
TA
Tstg
qJA
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (JunctiontoAmbient) (Note 4)
TGSD 516 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 lfpm
500 lfpm
QFN32
QFN32
$1.5
40 to +85
65 to +150
31
27
mA
°C
°C
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase)
Standard
Board
QFN32
12 °C/W
Tsol Wave Solder
PbFree
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Номер в каталогеОписаниеПроизводители
NB7L10082.5V / 3.3V 1:8 LVPECL Fanout BufferON Semiconductor
ON Semiconductor
NB7L1008MMulti-Level Inputs w/ Internal TerminationON Semiconductor
ON Semiconductor

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