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PDF NB7L72M Data sheet ( Hoja de datos )
| Número de pieza | NB7L72M | |
| Descripción | Multi-Level Inputs w/ Internal Termination | |
| Fabricantes | ON Semiconductor | |
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NB7L72M
2.5V / 3.3V Differential 2 x 2
Crosspoint Switch with
CML Outputs Clock/Data
Buffer/Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB7L72M is a high bandwidth, low voltage, fully differential
2 x 2 crosspoint switch with CML outputs. The NB7L72M design is
optimized for low skew and minimal jitter as it produces two identical
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
The differential IN/IN inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels (see
Figure 11). The 16 mA differential CML outputs provide matching
internal 50 W terminations and produce 400 mV output swings when
externally terminated with a 50 W resistor to VCC (see Figure 9).
The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and
is offered in a low profile 3x3 mm 16−pin QFN package. Application
notes, models, and support documentation are available at
www.onsemi.com.
The NB7L72M is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s
• Data Dependent Jitter < 10 ps pk−pk
www.Dat•aSMheaext4iUm.cuommInput Clock Frequency > 7 GHz
• Random Clock Jitter < 0.5 ps RMS, Max
• 150 ps Typical Propagation Delay
• 30 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV peak−to−peak, typical
• Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
• Internal 50 W Input Termination Resistors
• QFN−16 Package, 3mm x 3mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
72M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
+
SEL0
IN0
VT0
IN0
0 Q0
1 Q0
IN1 0
VT1
IN1 +
SEL1
1
Figure 1. Logic Diagram
Q1
Q1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 1
1
Publication Order Number:
NB7L72M/D
1 page  
NB7L72M
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min Typ
Max
Unit
fMAX
Maximum Input Clock Frequency
fDATAMAX
VOUTPP
Maximum Operating Data Rate (PRBS23)
Output Voltage Amplitude (@ VINPPmin)
(See Figures 3 and 10, Note 12)
VOUT w 250 mV
VOUT w 200 mV
fin ≤ 8.5 GHz
7.0
8.5
10
200 400
GHz
Gbps
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs,
@ 1GHz, Measured at Differential Cross−point
INn/INn to Qn/Qn 110 150 180
SELn to Qn/Qn
ps
tPLH TC
tSKEW
tDC
tjitter
Propagation Delay Temperature Coefficient
Output−to−Output Skew (within device) (Note 13)
Device−to−Device Skew (tpdmax – tpdmin)
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 8.5GHz
RJ – Output Random Jitter (Note 14)
DJ – Deterministic Jitter (Note 15)
fin v 8.5 GHz
v 10 Gbps
50 Dfs/°C
10 ps
20
45 50 55
%
0.2 0.5 ps RMS
10 ps pk−pk
VINPP
tr,, tf
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz (20% − 80%),
Q, Q
100 1200
25 30 50
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
500
450
400
www.DataSheet4U.com
350
300
Q AMP (mV)
250
200
0
1.0 2.0
3.0 4.0 5.0 6.0 7.0 8.0
fin, Clock Input Frequency (GHz)
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
VCC
INn
50 W
VTn
50 W
INn
Figure 4. Input Structure
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NB7L72M.PDF ] | |
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