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PDF NB7V58M Data sheet ( Hoja de datos )
| Número de pieza | NB7V58M | |
| Descripción | 1.8 V / 2.5 V / 3.3 V Differential 2:1 Clock / Data Multiplexer / Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB7V58M
1.8 V / 2.5 V / 3.3 V
Differential 2:1 Clock / Data
Multiplexer / Translator
with CML Outputs
Multi−Level Inputs w/ Internal
Termination
Description
The NB7V58M is a high performance differential 2−to−1 Clock or
Data multiplexer. The differential inputs incorporate internal 50 W
termination resistors that are accessed through the VT pin. This
feature allows the NB7V58M to accept various logic level standards,
such as LVPECL, CML or LVDS.
The NB7V58M produces minimal Clock or Data jitter operating up
to 7 GHz or 10.7 Gb/s, respectively. As such, the NB7V58M is ideal
for SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The 16 mA differential CML outputs provide matching internal
50 W terminations and 400 mV output swings when externally
terminated with a 50 W resistor to VCC.
The NB7V58M is offered in a low profile 3 mm x 3 mm 16−pin
QFN package and is a member of the GigaCommt family of high
performance Clock / Data products. For applications that require
equalization, the pin−compatible NB7VQ58M is also available.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
www.Dat•aSMheaext4iUm.cuommInput Data Rate > 10.7 Gb/s
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 7 GHz
• Random Clock Jitter < 0.8 ps RMS
• 180 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical
• Operating Range: VCC = 1.71 V to 3.6 V with GND = 0 V
• Internal 50 W Input Termination Resistors
• QFN−16 Package, 3 mm x 3 mm
• −40°C to +85°C Ambient Operating Temperature
• This is a Pb−Free Device
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7V
58M
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 0
1
Publication Order Number:
NB7V58M/D
1 page  
NB7V58M
Table 6. AC CHARACTERISTICS (VCC = 1.71 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C) (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
fDATAMAX
fSEL
Maximum Input Clock Frequency
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
Voutpp ≥ 200 mV
7
10.7
25
8
12
50
GHz
Gbps
MHz
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
(Note 12) (Figures 8 & 10)
fin ≤ 7 GHz 200
400
mV
tPLH,
tPHL
tPLH TC
tskew
tDC
tJITTER
FN
Propagation Delay to Differential Outputs,
@ 1 GHz, measured at differential cross−point
Propagation Delay Temperature Coefficient
Device − Device skew (tpdmax – tpdmin)
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
RJ – Output Random Jitter (Note 13)
DJ − Residual Output Deterministic Jitter (Note 14)
Phase Noise, fc = 1 GHz
INn/INn to Q, Q
SEL to Q, Q
120
5
fin v 5.0 GHz
fin v 7.0 GHz
fin v 7.0 GHz
fin v 10.7 Gbps
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
45
40
180
13
50
50
50
0.2
−135
−136
−150
−151
−151
−151
240 ps
22 ns
Dfs/°C
50 ps
55 %
60
0.8 ps RMS
10 ps pk−pk
dBc
t∫FN Integrated Phase Jitter (Figure 4) fc = 1 GHz, 12 kHz − 20 MHz Offset (RMS)
Crosstalk Induced Jitter (Adjacent Channel) (Note 15)
35 fs
0.7 ps RMS
VINPP
Input Voltage Swing (Differential Configuration) (Figure 10) (Note 16)
100
1200
mV
tr, tf Output Rise/Fall Times @ 1 GHz (20% − 80%)
Q, Q 15 35 50
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23 at 3 Gbps.
15. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
www.Dat1a6S.hIinneppeuut4ttsUv.o.cltoamge swing is a single−ended measurement operating in differential mode.
500 −115
−120
450
−125
400 −130
350 −135
−140
300
−145
250 −150
200
0 1 2 3 4 5 6 7 8 9 10
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typical)
−155
1.E+03
1.E+04 1.E+05 1.E+06 1.E+07
FREQUENCY OFFSET (Hz)
Figure 4. Typical Phase Noise
(VCC = 1.8 V, T = 255C, fc = 1 GHz)
1.E+08
http://onsemi.com
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