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PDF NB7L585 Data sheet ( Hoja de datos )
| Número de pieza | NB7L585 | |
| Descripción | 2.5 V / 3.3 V Differential 2:1 Mux Input To 1:6 LVPECL Clock/Data Fanout Buffer / Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB7L585
2.5V / 3.3V Differential 2:1
Mux Input to 1:6 LVPECL
Clock/Data Fanout Buffer /
Translator
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L585 is a differential 1:6 LVPECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585 produces six identical output copies of Clock or Data
operating up to 5 GHz or 8 Gb/s, respectively. As such, NB7L585 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The NB7L585 is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585 is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 8 Gb/s
• Data Dependent Jitter < 15 ps
• Maximum Input Clock Frequency > 5 GHz
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:6 LVPECL Outputs, 20 ps max
• 2:1 Multi−Level Mux Inputs
• 175 ps Typical Propagation Delay
• 55 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 800 mV peak−to−peak, typical
• Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• −40ºC to +85ºC Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
585
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
+
SEL
VREFAC0
IN0
50 W
VT0
50 W
IN0
0
Q0
Q0
Q1
Q1
Q2
IN1
50 W
VT1
50 W
IN1
VREFAC1
VCC
GND
1
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 2
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
1 Publication Order Number:
NB7L585/D
1 page  
NB7L585
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min Typ
Max
Unit
fMAX
fDATAMAX
fSEL
VOUTpp
Maximum Input Clock Frequency; VOUTpp w 400 mV
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
Output Voltage Amplitude (@ VINPPmin)
(Note 12) (Figures 8 and 10)
tPLH,
tPHL
tPLH TC
tskew
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
Propagation Delay Temperature Coefficient
Output − Output skew (within device) (Note 13)
Device − Device skew (tpd max – tpdmin)
57
GHz
8 10
Gbps
1.0 1.5
GHz
fin ≤ 4 GHz
fin ≤ 5 GHz
550 800
400 650
IN/IN to Q/Q 125 175 250
SEL to Q 75
200 300
mV
ps
50 Dfs/°C
20 ps
100
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fin v 5.0 GHz 45 50 55
%
FN Phase Noise, fin = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−135
−137
−149
−150
−150
−151
dBc
tŐFN
tJITTER
Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS)
RJ – Output Random Jitter (Note 14)
DJ − Residual Output Deterministic Jitter (Note 15)
fin ≤ 5.0 GHz
≤ 8 Gbps
36 fs
0.2 0.8 ps rms
5 15 ps pk−pk
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
0.7 psRMS
VINPP
tr,, tf
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q
100 1200
25 55 85
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC – 2 V. Input edge
rates 40 ps (20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
1000
800
Q AMP (mV)
600
400
200
0
01
23
456
78
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Clock Output Voltage Amplitude (VOUTpp) vs. Input Frequency (fin) at Ambient Temperature (Typical)
http://onsemi.com
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