NB7V585M PDF даташит
Спецификация NB7V585M изготовлена «ON Semiconductor» и имеет функцию, называемую «1.8 V / 2.5 V Differential 2:1 Mux Input To 1:6 CML Clock/Data Fanout Buffer/Translator». |
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Детали детали
Номер произв | NB7V585M |
Описание | 1.8 V / 2.5 V Differential 2:1 Mux Input To 1:6 CML Clock/Data Fanout Buffer/Translator |
Производители | ON Semiconductor |
логотип |
8 Pages
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NB7V585M
1.8V / 2.5V Differential 2:1
Mux Input to 1:6 CML
Clock/Data Fanout
Buffer/Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB7V585M is a differential 1−to−6 CML clock/data
distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50 W
termination resistors and will accept LVPECL, CML, or LVDS logic
levels (see Figure 9). The NB7V585M produces six identical output
copies of clock or data operating up to 6 GHz or 10 Gb/s, respectively.
As such, NB7V585M is ideal for SONET, GigE, Fiber Channel,
Backplane and other clock/data distribution applications. The 16 mA
differential CML output structure provides matching internal 50 W
source terminations, 400 mV output swings when externally
terminated with a 50 W resistor to VCC (see Figure 14) and is
optimized for low skew and minimal jitter. The NB7V585M is
powered with either 1.8 V or 2.5 V supply and is offered in a low
profile 5x5 mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7V585M is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz
• Random Clock Jitter < 0.8 ps RMS, Max
www.Dat•aSLheoewt4US.kceowm 1:6 CML Outputs, 20 ps Max
• 2:1 Multi−Level Mux Inputs
• 175 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential CML Outputs, 330 mV Peak−to−Peak, Typical
• Operating Range: VCC = 1.71 V to 1.89 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM*
1 32
1
QFN32
MN SUFFIX
CASE 488AM
NB7V
585M
AWLYYWW
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED LOGIC DIAGRAM
VCC
Q0
Q0
Q1
SEL Q1
VREFAC0
IN0
VT0
IN0
0
Q2
Q2
IN1
VT1
IN1
VREFAC1
VCC
GND
Q3
1 Q3
Q4
Q4
Q5
Q5
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
NB7V585M/D
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NB7V585M
Exposed Pad
(EP)
32 31 30 29 28 27 26 25
IN0 1
24 GND
VT0 2
23 VCC
VREFAC0 3
22 Q2
IN0 4
IN1 5
NB7V585M
21 Q2
20 Q3
VT1 6
19 Q3
VREFAC1 7
18 VCC
IN1 8
17
GND
9 10 11 12 13 14 15 16
Table 1. INPUT SELECT FUNCTION TABLE
SEL*
CLK Input Selected
0 IN0
1 IN1
*Defaults HIGH when left open.
Figure 1. 32−Lead QFN Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1,4 IN0, IN0 LVPECL, CML, Non−inverted, Inverted, Differential Inputs
5,8
IN1, IN1
LVDS Input
2,6 VT0, VT1
Internal 100 W Center−tapped Termination Pin for IN0/IN0 and IN1/IN1
31 SEL LVTTL/LVCMOS Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open
Input
10 NC
− No Connect
11, 16, 18
23, 25, 30
VCC
− Positive Supply Voltage.
29, 28
27, 26
Q0, Q0
Q1, Q1
CML Output
Non−inverted, Inverted Differential Outputs (Note 1).
www.DataSh22e20e,,t421U19 .com
Q2, Q2
Q3, Q3
CML Output
Non−inverted, Inverted Differential Outputs (Note 1).
15, 14
13, 12
Q4, Q4
Q5, Q5
CML Output
Non−inverted, Inverted Differential Outputs (Note 1).
9, 17,
24, 32
GND
Negative Supply Voltage, connected to Ground
3 VREFAC0 − Output Voltage Reference for Capacitor−Coupled Inputs, only
7 VREFAC1
− EP
− The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electric-
ally and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then, the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source
termination resistors.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7V585M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Input Pullup Resistor (RPU)
Moisture Sensitivity (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Value
> 4 kV
> 200 V
75 kW
Level 1
UL 94 V−0 @ 0.125 in
308
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
VIO
VINPP
IIN
IOUT
Positive Power Supply
Input/Output Voltage
Differential Input Voltage |INx − INx|
Input Current Through RT (50 W Resistor)
Output Current
GND = 0 V
GND = 0 V
Continuous
Surge
−0.5 v VIO v VCC + 0.5
3.0
−0.5 to VCC + 0.5
1.89
$40
34
40
V
V
V
mA
mA
IVFREFAC
TA
Tstg
qJA
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−32
QFN−32
$1.5
−40 to +85
−65 to +150
31
27
mA
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
QFN−32
(Note 4)
12 °C/W
Tsol Wave Solder
Pb−Free
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
www.Dat4a.ShJeEeDt4EUC.csotamndard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
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Номер в каталоге | Описание | Производители |
NB7V585M | 1.8 V / 2.5 V Differential 2:1 Mux Input To 1:6 CML Clock/Data Fanout Buffer/Translator | ON Semiconductor |
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