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PDF NB7L585R Data sheet ( Hoja de datos )
| Número de pieza | NB7L585R | |
| Descripción | 2.5V/3.3V 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer | |
| Fabricantes | On Semiconductor | |
| Logotipo |  |
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NB7L585R
2.5V/3.3V, 7GHz/10Gbps
Differential 2:1 Mux Input to
1:6 RSECL Clock/Data
Fanout Buffer / Translator
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L585R is a differential 1:6 RSECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585R produces six identical output copies of Clock or
Data operating up to 7 GHz or 10 Gb/s, respectively. As such,
NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock/Data distribution applications.
The NB7L585R is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585R is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 7 GHz Typical
www.Dat•aSRheaent4dUom.coCmlock Jitter < 0.8 ps RMS
• Low Skew 1:6 RSECL Outputs, 20 ps max
• 2:1 Multi−Level Mux Inputs
• 160 ps Typical Propagation Delay
• 40 ps Typical Rise and Fall Times
• Differential RSECL Outputs, 400 mV peak−to−peak, typical
• Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• −40ºC to +85ºC Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
585R
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
+
SEL
VREFAC0
IN0
VT0
50 W
50 W
IN0
0
Q0
Q0
Q1
Q1
Q2
IN1
VT1
50 W
50 W
IN1
VREFAC1
VCC
GND
1
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 0
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
1 Publication Order Number:
NB7L585R/D
1 page  
NB7L585R
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min Typ
Max
Unit
fMAX
fDATAMAX
fSEL
VOUTpp
Maximum Input Clock Frequency; VOUTpp w 200 mV
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
Output Voltage Amplitude (@ VINPPmin)
(Note 12) (Figures 8 and 10)
fin ≤ 6.0 GHz
67
8 10
1.0 1.5
200 400
GHz
Gbps
GHz
mV
tPLH,
tPHL
tPLH TC
tskew
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
Propagation Delay Temperature Coefficient
Output − Output skew (within device) (Note 13)
Device − Device skew (tpd max – tpdmin)
IN/IN to Q/Q 100 160 225
SEL to Q
200 300
ps
50 Dfs/°C
20 ps
100
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fin v 6.0 GHz
45
50 55
%
FN Phase Noise, fc = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−134
−136
−149
−150
−150
−151
dBc
tŐFN
tJITTER
Integrated Phase Jitter (Figure x) fc = 1 GHz, 12 kHz * 20 MHz Offset (RMS)
RJ – Output Random Jitter (Note 14)
DJ − Residual Output Deterministic Jitter (Note 15)
fin ≤ 5.0 GHz
≤ 8 Gbps
36 fs
0.2 0.8 ps RMS
2.0 10 ps pk−pk
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
0.7 ps RMS
VINPP
tr,, tf
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q
100 1200
15 40 70
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC – 2 V. Input edge
rates 40 ps (20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
www.Dat11a54S..hAAeddeddtii4ttiiUvvee.cPRomeMaSk−jittote−rPweiathk
50%
data
duty cycle clock
dependent jitter
signal.
with input
NRZ
data
at
PRBS23.
16. Input voltage swing is a single−ended measurement operating in differential mode.
17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
500
Q AMP (mV)
400
300
200
100
00 1
23
456
78
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Clock Output Voltage Amplitude (VOUTpp) vs. Input Frequency (fin) at Ambient Temperature (Typical)
http://onsemi.com
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet NB7L585R.PDF ] | |
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