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PDF NB7V33M Data sheet ( Hoja de datos )
| Número de pieza | NB7V33M | |
| Descripción | 1.8V / 2.5V 10GHz Div By 4 Clock Divider | |
| Fabricantes | ON Semiconductor | |
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NB7V33M
1.8V / 2.5V, 10GHz ÷4 Clock
Divider with CML Outputs
Multi−Level Inputs w/ Internal Termination
Description
The NB7V33M is a differential B4 Clock divider with
asynchronous reset. The differential Clock inputs incorporate internal
50 W termination resistors and will accept LVPECL, CML and LVDS
logic levels. The NB7V33M produces a ÷4 output copy of an input
Clock operating up to 10 GHz with minimal jitter. The Reset pin is
asserted on the rising edge. Upon powerup, the internal flip*flops
will attain a random state; the Reset allows for the synchronization of
multiple NB7V33M’s in a system. The 16 mA differential CML
output provides matching internal 50 W termination which guarantees
400 mV output swing when externally receiver terminated with 50 W
to VCC.
The NB7V33M is the B4 version of the NB7V32M (B2) and is
offered in a low profile 3mm x3 mm 16−pin QFN package.
The NB7V33M is a member of the GigaComm™ family of high
performance clock products. Application notes, models, and support
documentation are available at www.onsemi.com.
Features
• Maximum Input Clock Frequency > 10 GHz, typical
• 260 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical
• Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V
www.Dat•aSIhneteetr4nUa.lco5m0 W Input Termination Resistors
• Random Clock Jitter < 0.8 ps RMS
• QFN−16 Package, 3mm x 3mm
• −40ºC to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7V
33M
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
R
VTCLK
50 W
CLK
CLK
50 W
VTCLK
RESET
B4
Q0
Q0
VREFAC
VCC
GND
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 1
1
Publication Order Number:
NB7V33M/D
1 page  
NB7V33M
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min Typ
Max
Unit
fMAX
VOUTPP
Maximum Input Clock Frequency
Output Voltage Amplitude (@ VINPPmin) fin ≤ 10 GHz
(Note 12) (Figure 3)
10 11
260 400
GHz
mV
tPLH,
tPHL
tPLH TC
tskew
Propagation Delay to Differential Outputs,
@ 1 GHz, measured at differential crosspoint
Propagation Delay Temperature Coefficient
Duty Cycle Skew (Note 13)
Device − Device skew (tpdmax – tpdmin)
CLK/CLK to Q, Q 150 200 350
R to Q, Q 500 600 700
ps
50 Dfs/°C
20 ps
50
tRR Reset Recovery (See Figure 16)
tPW Minimum Pulse Width R
tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 10 GHz
fN Phase Noise, fc = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
550 135
500 200
45 50
−144
−147
−152
−152
−152
−153
55
ps
ps
%
dBc
tŘfN
tJITTER
VINPP
tr, tf
Integrated Phase Jitter (Figure x) fc = 1 GHz, 12 kHz − 20 MHz Offset
RJ – Output Random Jitter (Note 14) fin v 10.0 GHz
Input Voltage Swing (Differential Configuration) (Figure 11) (Note 15)
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q
35 fs
0.2 0.8 ps RMS
200
1200
mV
20 35 60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 1 GHz, VINPPmin, 50% duty−cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point
of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. Skew
is measured between outputs under identical transitions and conditions.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Input voltage swing is a single−ended measurement operating in differential mode.
www.DataSheet4U.com
500
450
400
350
300
250
200
0 2 4 6 8 10
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
http://onsemi.com
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