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W29C010 PDF даташит

Спецификация W29C010 изготовлена ​​​​«Winbond» и имеет функцию, называемую «128K X 8 CMOS FLASH MEMORY».

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Номер произв W29C010
Описание 128K X 8 CMOS FLASH MEMORY
Производители Winbond
логотип Winbond логотип 

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W29C010 Даташит, Описание, Даташиты
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W29C010
128K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29C010 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29C010 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt program and erase operations
Fast page-write operations
128 bytes per page
Page program cycle: 10 mS (max.)
Effective byte-program cycle time: 39 µS
Optional software-protected data write
Fast chip-erase operation: 50 mS
Read access time: 45/70/90 nS
Typical page program/erase cycles: 1K/10K
Ten-year data retention
Software and hardware data protection
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program timing with internal VPP
generation
End of program detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP, 450
mil SOP, TSOP and PLCC
Publication Release Date: April 1997
- 1 - Revision A1









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W29C010 Даташит, Описание, Даташиты
PIN CONFIGURATIONS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
DIP
32 VDD
31 WE
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
AAA
V/
1 1 1 N D WN
2 5 6 CD E C
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 32-pin 26
9 PLCC 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
D D GD D D D
QQN QQQQ
1 2D3 4 5 6
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W29C010
BLOCK DIAGRAM
VDD
VSS
CE
OE CONTROL
WE
OUTPUT
BUFFER
D.Q0
.
DQ7
A0
. DECODER
.
A16
CORE
ARRAY
PIN DESCRIPTION
SYMBOL
PIN NAME
A0A16
DQ0DQ7
CE
OE
WE
VDD
GND
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
-2-









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W29C010 Даташит, Описание, Даташиты
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W29C010
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C010 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Page Write Mode
The W29C010 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200
µS, after the initial byte-load cycle, the W29C010 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional byte is loaded into the page buffer within 300 µS (TBLCO)
from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last
rising edge of WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer
must have the same page address. A0 to A6 specify the byte address within the page. The bytes may
be loaded in any order; sequential loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to
a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.
The W29C010 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
Publication Release Date: April 1997
- 3 - Revision A1










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