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PDF SA25F020 Data sheet ( Hoja de datos )
| Número de pieza | SA25F020 | |
| Descripción | 2Mb Serial Flash | |
| Fabricantes | Saifun | |
| Logotipo |  |
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Features
•= Saifun NROM™ Flash Cell
•= Serial Peripheral Interface (SPI) Compatible,
Supports SPI Modes 0 (0,0) and 3 (1,1)
•= Page Program Operation:
– 1024 pages (256 Bytes/Page)
– Single Page Rewrite Cycle (Erase and Program) in 10ms
Typical
•= Page Program Mode (up to 256 bytes) in 8ms Typical
•= Page Erase (256 bytes) in 3 ms
•= Sector Erase (512 Kb) in 0.5 s
•= Bulk Erase (2 Mb)
•= Single Supply Voltage: 2.7 V to 3.6 V
•= 25MHz Clock Rate
•= Block Write Protection: Protect Quarter, Half or Entire Array
•= Write Protect Pin and Write Disable Instructions of Both
Hardware and Software Data Protection
•= 100,000 Erase Cycles (Minimum)
•= More than 20-Year Data Retention
•= Low-power Standby Current (less than 1µA)
•= 8-SOIC Narrow Package
•= MLF Leadless Package
•= Temperature Range:
– Industrial: -40°C to +85°C
– Commercial: 0°C to +70°C
SA25F020
Advanced
Information
2Mb Serial Flash
with 25MHz SPI Bus
Interface
http://www.saifun.com
Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.
This Data Sheet states Saifun's current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 1986 Rev: 1 Amendment: 0
Issue Date: 24 July 2003
1 page  
SA25F020
Awdwvawn.cDeadtIanSfohremeatt4ioUn.com
SAIFUN
5
Memory Organization
The memory is organized in the following
manner:
•= 262,144 bytes (8 bits each)
•= 4 sectors (512 Kb, 65,536 bytes
each), as shown in Table 1
Each page can be individually
programmed, with the bits programmed
from 1 to 0. The SA25F020's memory can
be erased via the Page, Sector or Bulk
Erase commands, with the bits erased
from 0 to 1.
•= 1024 pages (256 bytes each)
Table 1. Memory Organization
Sector
Address Range
3
30000h
3FFFFh
2
20000h
2FFFFh
1
10000h
1FFFFh
0
00000h
0FFFFh
SRAM
PS
Logic
Array - L
X
D
E
Array - R
C
RD DATA PATH
IO
Figure 1. SA25F020 Block Diagram
5 Page 
Timing Diagrams
All timing diagrams are based on SPI protocol modes 0 and 1.
SA25F020 Awdwvawn.cDeadtIanSfohSreAmeIaFttU4ioUNn.com11
CS
SCK
SI
SO
tCSH
tCSS
tCS
tCSH
tCSS
tSU:DAT tHD:DAT
MSB IN
tCRT
tCFT
LSB IN
High Impedance
Figure 4. SPI Mode 0 (0,0) Input Timing
CS
SCK
SO
tV
tHO
tWH
tV
tHO
tWL
LSB OUT
tDIS
Figure 5. SPI Mode 0 (0,0) Output Timing
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SA25F020.PDF ] | |
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