PDF HYMD232M726A8-M Data sheet ( Hoja de datos )

Número de pieza	HYMD232M726A8-M
Descripción	Unbuffered DDR SO-DIMM
Fabricantes	Hynix Semiconductor
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No Preview Available ! DESCRIPTION www.DataSheet4U.com 32Mx72 bits Unbuffered DDR SO-DIMM HYMD232M726A(L)8-J/M/K/H/L Hynix HYMD232M726A(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Out- line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232M726A(L)8-J/M/K/H/L series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate. Hynix HYMD232M726A(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchro- nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD232M726A(L)8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func- tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • 256MB (32M x 72) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRAM • Data inputs on DQS centers when write (centered DQ) • JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) • Data strobes synchronized with output data for read and input data for write • 2.5V +/- 0.2V VDD and VDDQ Power supply • Programmable CAS Latency 2 / 2.5 supported • All inputs and outputs are compatible with SSTL_2 interface • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz/166MHz • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • tRAS Lock-out function supported • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock ORDERING INFORMATION Part No. HYMD232M726A(L)8-J HYMD232M726A(L)8-M HYMD232M726A(L)8-K HYMD232M726A(L)8-H HYMD232M726A(L)8-L Power Supply VDD=2.5V VDDQ=2.5V Clock Frequency 166MHz (DDR333) 133MHz (DDR266:2-2-2) 133MHz (DDR266A) 133MHz (DDR266B) 100MHz (DDR200) Interface SSTL_2 Form Pactor 200pin Unbuffered SO-DIMM JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2/Oct. 02 1 1 page CAPACITANCE (TA=25oC, f=100MHz ) www.DataSheet4U.com HYMD232M726A(L)8-J/M/K/H/L Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance Data Input / Output Capacitance Pin A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0, CKE1 /CS0, /CS1 CK0, /CK0, CK1, /CK1 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 CB0 ~ CB7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIO1 CIO2 Min TBD TBD TBD TBD TBD TBD TBD TBD Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Max TBD TBD TBD TBD TBD TBD TBD TBD Unit pF pF pF pF pF pF pF pF Output VTT RT=50Ω Zo=50Ω CL=30pF VREF Rev. 0.2/Oct. 02 5 5 Page www.DataSheet4U.com HYMD232M726A(L)8-J/M/K/H/L - continued - Parameter Symbol Write DQS Low Level Width tDQSL Clock to First Rising edge of DQS-In tDQSS Data-In Setup Time to DQS-In (DQ & DM) tDS Data-in Hold Time to DQS-In (DQ & DM) tDH DQ & DM Input Pulse Width tDIPW Read DQS Preamble Time tRPRE Read DQS Postamble Time tRPST Write DQS Preamble Setup Time tWPRES Write DQS Preamble Hold Time tWPREH Write DQS Postamble Time tWPST Mode Register Set Delay tMRD Exit Self Refresh to Any Execute Command tXSC Average Periodic Refresh Interval tREFI DDR266A Min Max 0.35 - 0.75 1.25 0.45 - 0.45 - 1.75 - 0.9 1.1 0.4 0.6 0- 0.25 - 0.4 0.6 2- 200 - - 15.6 DDR266B Min Max 0.35 - 0.75 1.25 0.45 - 0.45 - 1.75 - 0.9 1.1 0.4 0.6 0- 0.25 - 0.4 0.6 2- 200 - - 15.6 DDR200 Min Max 0.35 - 0.72 1.28 0.5 - 0.5 - 1.75 - 0.9 1.1 0.4 0.6 0- 0.25 - 0.4 0.6 2- 200 - - 15.6 Unit Note CK CK ns 6,7, ns 11~13 ns CK CK CK CK CK CK CK 8 us Rev. 0.2/Oct. 02 11 11 Page

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