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PDF SE97 Data sheet ( Hoja de datos )
| Número de pieza | SE97 | |
| Descripción | DDR memory module temp sensor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SE97 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SE97
www.DataSheet4U.com
DDR memory module temp sensor with integrated SPD, 3.3 V
Rev. 07 — 29 January 2010
Product data sheet
1. General description
The NXP Semiconductors SE97 measures temperature from −40 °C to +125 °C with
JEDEC Grade B ±1 °C accuracy between +75 °C and +95 °C and also provide 256 bytes
of EEPROM memory communicating via the I2C-bus/SMBus. It is typically mounted on a
Dual In-line Memory Module (DIMM) measuring the DRAM temperature in accordance
with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature Sensor
Component specification and also replacing the Serial Presence Detect (SPD) which is
used to store memory module and vendor information.
The SE97 thermal sensor operates over the VDD range of 3.0 V to 3.6 V and the EEPROM
over the range of 3.0 V to 3.6 V write and 1.7 V to 3.6 V read.
Placing the Temp Sensor (TS) on a DIMM allows accurate monitoring of the DIMM module
temperature to better estimate the DRAM case temperature (Tcase) to prevent it from
exceeding the maximum operating temperature of 85 °C. The chip set throttles the
memory traffic based on the actual temperatures instead of the calculated worst-case
temperature or the ambient temperature using a temp sensor mounted on the
motherboard. There is up to 30 % improvement in thin and light notebooks that are using
one or two 1 GB SO-DIMM modules. The TS is required on DDR3 RDIMM and RDIMM
ECC. Future uses of the TS will include more dynamic control over thermal throttling, the
ability to use the Alarm Window to create multiple temperature zones for dynamic
throttling and to save processor time by scaling the memory refresh rate.
The TS consists of a ΔΣ Analog-to-Digital Converter (ADC) that monitors and updates its
own temperature readings 10 times per second, converts the reading to a digital data, and
latches them into the data temperature register. User-programmable registers, the
specification of upper/lower alarm and critical temperature trip points, EVENT output
control, and temperature shutdown, provide flexibility for DIMM temperature-sensing
applications.
When the temperature changes beyond the specified boundary limits, the SE97 outputs
an EVENT signal using an open-drain output that can be pulled up between 0.9 V and
3.6 V. The user has the option of setting the EVENT output signal polarity as either an
active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can even be configured as a critical temperature output.
The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes
(address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write
Protected (RWP) by software. This allows DRAM vendor and product information to be
stored and write protected. The upper 128 bytes (address 80h to FFh) are not write
protected and can be used for general purpose data storage.
1 page  
NXP Semiconductors
SE97www.DataSheet4U.com
DDR memory module temp sensor with integrated SPD, 3.3 V
6. Pinning information
6.1 Pinning
A0 1
A1 2
A2 3
VSS 4
SE97PW
8 VDD
7 EVENT
6 SCL
5 SDA
002aab805
Fig 2. Pin configuration for TSSOP8
terminal 1
index area
A0 1
A1 2
A2 3
SE97TL
8 VDD
7 EVENT
6 SCL
VSS 4
5 SDA
002aad548
Transparent top view
Fig 3. Pin configuration for HXSON8
terminal 1
index area
A0 1
A1 2
A2 3
VSS 4
SE97TK
8 VDD
7 EVENT
6 SCL
5 SDA
002aab803
Transparent top view
Fig 4. Pin configuration for HVSON8
terminal 1
index area
A0 1
A1 2
A2 3
SE97TP
8 VDD
7 EVENT
6 SCL
VSS 4
5 SDA
002aad768
Transparent top view
Fig 5. Pin configuration for HWSON8
(SOT1069-1)
terminal 1
index area
A0 1
A1 2
SE97TP/S900
8 VDD
7 EVENT
A2 3
VSS 4
6 SCL
5 SDA
002aaf007
Transparent top view
Fig 6. Pin configuration for HWSON8 (SOT1069-2)
SE97_7
Product data sheet
Rev. 07 — 29 January 2010
© NXP B.V. 2010. All rights reserved.
5 of 55
5 Page 
NXP Semiconductors
SE97www.DataSheet4U.com
DDR memory module temp sensor with integrated SPD, 3.3 V
– Competitor devices: Compares the Alarm Window with temperature register at any
time, so they get the EVENT output immediately when new Tth(crit) and EVENT
output are set at the same time.
– Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1).
Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before
EVENT output is enabled and Event value is checked.
1. Set Tth(crit).
2. Doing something else (make sure that exceeds 125 ms).
3. Enable the EVENT output (EOCTL = 1).
4. Wait 20 μs.
5. Read Event value.
– SE97B will compare alarm window and temperature register immediately.
7.3.3 EVENT operation modes
7.3.3.1 Comparator mode
In comparator mode, the EVENT output behaves like a window-comparator output that
asserts when the temperature is outside the window (e.g., above the value programmed in
the Upper Boundary Alarm Trip register or below the value programmed in the Lower
Boundary Alarm Trip register or above the Critical Alarm Trip resister if Tth(crit) only is
selected). Reads/writes on the registers do not affect the EVENT output in comparator
mode. The EVENT signal remains asserted until the temperature goes inside the alarm
window or the window thresholds are reprogrammed so that the current temperature is
within the alarm window.
The comparator mode is useful for thermostat-type applications, such as turning on a
cooling fan or triggering a system shutdown when the temperature exceeds a safe
operating range.
7.3.3.2 Interrupt mode
In interrupt mode, EVENT asserts whenever the temperature crosses an alarm window
threshold. After such an event occurs, writing a 1 to the Clear EVENT bit (CEVNT) in the
configuration register de-asserts the EVENT output until the next trigger condition occurs.
In interrupt mode, EVENT asserts when the temperature crosses the alarm upper
boundary. If the EVENT output is cleared and the temperature continues to increase until
it crosses the critical temperature threshold, EVENT asserts again. Because the
temperature is greater than the critical temperature threshold, a Clear EVENT command
does not clear the EVENT output. Once the temperature drops below the critical
temperature, EVENT de-asserts immediately.
• Advisory note:
– NXP device: If the EVENT output is not cleared before the temperature goes
above the critical temperature threshold EVENT de-asserts immediately when
temperature drops below the critical temperature.
– Competitor devices: If the EVENT output is not cleared before or when the
temperature is in the critical temperature threshold, EVENT will remain asserted
after the temperature drops below the critical temperature until a Clear EVENT
command.
SE97_7
Product data sheet
Rev. 07 — 29 January 2010
© NXP B.V. 2010. All rights reserved.
11 of 55
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SE97.PDF ] | |
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