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PDF SCAN90004 Data sheet ( Hoja de datos )
| Número de pieza | SCAN90004 | |
| Descripción | 4-Channel LVDS Buffer/Repeater | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 2005
www.DataSheet4U.com
SCAN90004
4-Channel LVDS Buffer/Repeater
with Pre-Emphasis and IEEE 1149.6
General Description
The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/
repeater. High speed data paths and flow-through pinout
minimize internal device jitter and simplify board layout,
while configurable pre-emphasis overcomes ISI jitter effects
from lossy backplanes and cables. The differential inputs
interface to LVDS, and Bus LVDS signals such as those on
National’s 10-, 16-, and 18- bit Bus LVDS SerDes, as well as
CML and LVPECL. The differential inputs and outputs are
internally terminated with a 100Ω resistor to improve perfor-
mance and minimize board space. The repeater function is
especially useful for boosting signals for longer distance
transmission over lossy cables and backplanes.
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports
testability of both single-ended LVTTL/CMOS and high-
speed differential LVDS interconnects. The 3.3V supply,
CMOS process, and LVDS I/O ensure stable high perfor-
mance at low power over the entire industrial -40 to +85˚C
temperature range.
Features
n 1.5 Gbps data rate per channel
n Configurable pre-emphasis drives lossy backplanes and
cables
n Low output skew and jitter
n Hot plug protection
n LVDS/CML/LVPECL compatible input, LVDS output
n On-chip 100Ω input and output termination
n 15 kV ESD protection on LVDS inputs and outputs
n IEEE 1149.1 and 1149.6 compliant
n Fault Insertion
n Single 3.3V supply
n Very low power consumption
n Industrial -40 to +85˚C temperature range
n Small TQFP Package Footprint
n Evaluation Kit Available
n See DS90LV004 for non-JTAG version
20113001
SCAN90004 Block Diagram
© 2005 National Semiconductor Corporation DS201130
Pinout - Top View
20113002
www.national.com
1 page  
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
SWITCHING CHARACTERISTICS — SCAN FEATURES
fMAX
Maximum TCK Clock
Frequency
tS
tH
tS
tH
tW
tW
tREC
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to TCK
RL = 500Ω,
CL = 35 pF
www.DataSheet4U.com
Typ
Min Max
(Note 4)
Units
25.0
3.0
0.5
2.5
0.5
10.0
2.5
1.0
MHz
ns
ns
ns
ns
ns
ns
ns
Note 4: Typical parameters are measured at VDD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested.
Note 5: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Note 6: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at
750MHz, tr = tf = 50ps (20% to 80%).
Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps,
tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage
= VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%).
5 www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SCAN90004.PDF ] | |
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