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CAT5251 PDF даташит

Спецификация CAT5251 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «Quad Digitally Programmable Potentiometer».

Детали детали

Номер произв CAT5251
Описание Quad Digitally Programmable Potentiometer
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT5251 Даташит, Описание, Даташиты
CAT5251www.DataSheet4U.com
Quad Digitally Programmable Potentiometer (DPP™) with
256 Taps and SPI Interface
FEATURES
„ Four linear-taper digitally programmable
potentiometers
„ 254 resistor taps per potentiometer
„ End to end resistance 50kor 100k
„ Potentiometer control and memory access via
SPI interface
„ Low wiper resistance, typically 100
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ SOIC 24-lead and TSSOP 24-lead
„ Industrial temperature range
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC 24-Lead (W)
TSSOP 24-Lead (Y)
DESCRIPTION
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of resistive elements connected between
two externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
FUNCTIONAL DIAGRAM
SO 1
24 H¯¯O¯L¯D¯
A0 2
23 SCK
RW3
RH3
RL3
NC
VCC
RLO
RHO
RWO
¯C¯S¯
3 22
4 21
5 20
6 CAT 19
7 5251 18
8 17
9 16
10 15
11 14
RL2
RH2
RW2
NC
GND
RW1
RH1
RL1
A1
¯W¯P¯ 12
13 SI
CS
SCK
SI
SO
WP
A0
A1
HOLD
SPI BUS
INTERFACE
CONTROL
LOGIC
RH0 RH1 RH2 RH3
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
RW0
RW1
RW2
RW3
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2017 Rev. F









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CAT5251 Даташит, Описание, Даташиты
CAT5251
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of four devices
can be addressed on a single bus. A match in the
slave address must be made with the address input
in order to initiate communication with the CAT5251.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical
potentiometer.
RW: Wiper
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
¯C¯S¯: Chip Select
¯C¯S¯ is the Chip select pin. ¯C¯S¯ low enables the
CAT5251 and ¯C¯S¯ high disables the CAT5251. ¯C¯S¯
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on ¯C¯S¯ is required prior to any
sequence being initiated. A low to high transition on
¯C¯S¯ after a valid write sequence is what initiates an
internal write cycle.
¯W¯P¯: Write Protect
¯W¯P¯ is the Write Protect pin. The Write Protect pin
will allow normal read/write operations when held
high. When ¯W¯P¯ is tied low, all non-volatile write
operations to the Data registers are inhibited
(change of wiper control register is allowed). ¯W¯P¯
going low while ¯C¯S¯ is still low will interrupt a write to
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the registers. If the internal write cycle has already
been initiated, ¯W¯P¯ going low will have no effect on
any write operation.
H¯¯O¯L¯D¯: Hold
The ¯H¯O¯L¯D¯ pin is used to pause transmission to the
CAT5251 while in the middle of a serial sequence
without having to re-transmit entire sequence at a
later time. To pause, H¯¯O¯L¯D¯ must be brought low
while SCK is low. The SO pin is in a high impedance
state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, H¯¯O¯L¯D¯ is brought high, while SCK is
low. (H¯¯O¯L¯D¯ should be held high any time this
function is not being used.) H¯¯O¯L¯D¯ may be tied high
directly to VCC or tied to VCC through a resistor.
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
SO
A0
RW3
RH3
RL3
NC
VCC
RL0
RH0
RW0
¯C¯S¯
¯W¯P¯
SI
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCK
H¯¯O¯L¯D¯
Function
Serial Data Output
Device Address, LSB
Wiper Terminal for Potentiometer 3
High Reference Terminal for
Potentiometer 3
Low Reference Terminal for
Potentiometer 3
No Connect
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
Wiper Terminal for Potentiometer 2
High Reference Terminal for
Potentiometer 2
Low Reference Terminal for
Potentiometer 2
Bus Serial Clock
Hold
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
Doc. No. MD-2017 Rev. F









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CAT5251 Даташит, Описание, Даташиты
SERIAL BUS PROTOCOL
The CAT5251 supports the SPI bus data
transmission protocol. The synchronous Serial
Peripheral Interface (SPI) helps the CAT5251 to
interface directly with many of today's popular
microcontrollers. The CAT5251 contains an 8-bit
instruction register. The instruction set and the
operation codes are detailed in Table 3, Instruction
Set on page 8.
After the device is selected with ¯C¯S¯ going low the
first byte will be received. The part is accessed via
the SI pin, with data being clocked in on the rising
edge of SCK. The first byte contains one of the six
op-codes that define the operation to be performed.
ABSOLUTE MAXIMUM RATINGS (1)
Parameter
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS(2)(3)
VCC with Respect to Ground
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Wiper Current
Recommended Operating Conditions
VCC = +2.5V to +6V
Parameter
Operating Ambient Temperature (Industrial)
DEVICE OPERATION
CAT5251
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The CAT5251 is four resistor arrays integrated with an
SPI serial interface logic, four 8-bit wiper control
registers and sixteen 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL). RH and RL
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series
resistors are connected to the output wiper terminals
(RW) by a CMOS transistor switch. Only one tap point
for each potentiometer is connected to its wiper terminal
at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data
registers via the SPI bus. Additional instructions allow
data to be transferred between the wiper control
registers and each respective potentiometer's non-
volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC +2.0
-2.0 to +7.0
1.0
300
±6
Units
°C
°C
V
V
W
°C
mA
Ratings
-40 to +85
Units
°C
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2017 Rev. F










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