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PDF 74LVCV2G66 Data sheet ( Hoja de datos )
| Número de pieza | 74LVCV2G66 | |
| Descripción | Overvoltage tolerant bilateral switch | |
| Fabricantes | NXP Semiconductors | |
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74LVCV2G66
Overvoltage tolerant bilateral switch
Rev. 01 — 2 April 2004
www.DataSheet4U.com
Product data sheet
1. General description
The 74LVCV2G66 is a high-performance, low-power, low-voltage, Si-gate CMOS device
that provides superior performance to most advanced CMOS compatible TTL families.
The 74LVCV2G66 provides two single pole, single throw analog or digital switches. Each
switch includes an overvoltage tolerant input/output terminal (pin nZ), an output/input
terminal (pin nY) and low-power active HIGH enable input (pin nE).
The overvoltage tolerant switch terminals allow the switching of signals in excess of VCC.
The low-power enable input eliminates the necessity of using current limiting resistors in
portable applications when using control logic signals much lower than VCC. These inputs
are also overvoltage tolerant.
2. Features
s Wide supply voltage range from 2.3 V to 5.5 V
s Ultra low-power operation
s Very low ON-resistance:
x 8.0 Ω (typ) at VCC = 2.7 V
x 7.5 Ω (typ) at VCC = 3.3 V
x 7.3 Ω (typ) at VCC = 5.0 V.
s 5 V tolerant input for interfacing with 5 V logic
s High noise immunity
s Switch handling capability of 32 mA
s CMOS low-power consumption
s Latch-up performance exceeds 250 mA
s Incorporates overvoltage tolerant analog switch technology
s Switch accepts voltages up to 5.5 V independent of VCC
s SOT505-2 and SOT765-1 package
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; tr = tf ≤ 2.5 ns; min and max at Tamb = −40 °C to +85 °C; typical at Tamb = 25 °C.
Symbol Parameter
Conditions
Min Typ Max Unit
tPZH, tPZL turn-on time E to
Y or Z
CL = 50 pF; RL = 500 Ω
VCC = 3.0 V to 3.6 V
1.0 3.8 7.5 ns
VCC = 4.5 V to 5.5 V
1.0 2.7 5.0 ns
1 page  
Philips Semiconductors
74LVCV2G66www.DataSheet4U.com
Overvoltage tolerant bilateral switch
10. Recommended operating conditions
Table 7: Recommended operating conditions
Symbol Parameter
Conditions
Min Typ Max Unit
VCC supply voltage
2.3 -
VI input voltage
0-
VS
DC switch voltage
enable and disable [1] 0
-
range
mode
5.5 V
5.5 V
5.5 V
Tamb
operating ambient
temperature
−40 -
+125 °C
tr, tf input rise and fall times VCC = 2.3 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 5.5 V 0 -
10 ns/V
[1] To avoid drawing VCC current out of terminal nZ when switch current flows in terminal nY, the voltage drop
across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC
current will flow out of terminal nY. In this case, there is no limit for the voltage drop across the switch.
11. Static characteristics
Table 8: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Min Typ
Tamb = −40 °C to +85 °C [1]
VIH HIGH-level input
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.6 × VCC -
2.0 -
0.55 × VCC -
VIL
LOW-level input
VCC = 2.3 V to 2.7 V
voltage
VCC = 3.0 V to 3.6 V
--
--
ILI
IS(OFF)
input leakage current
analog switch
OFF-state current per
channel
VCC = 4.5 V to 5.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VS = 0 V or 5.5 V;
VCC = 2.3 V to 5.5 V;
see Figure 5
-
-
[2] -
-
±0.1
±0.1
IS(ON)
analog switch
ON-state current per
channel
VS = 0 V or 5.5 V;
VCC = 2.3 V to 5.5 V;
see Figure 6
[2] -
±0.1
ICC
∆ICC
CI
quiescent supply
current
additional quiescent
supply current per pin
input capacitance
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.0 V to 5.5 V
- 0.1
- 0.1
- 2.5
CS switch capacitance OFF-state
- 8.0
ON-state
- 16
Max Unit
-V
-V
-V
0.1 × VCC V
0.5 V
0.15 × VCC V
±5 µA
±10 µA
±10 µA
10 µA
5 µA
- pF
- pF
- pF
9397 750 13027
Product data sheet
Rev. 01 — 2 April 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 23
5 Page 
Philips Semiconductors
74LVCV2G66www.DataSheet4U.com
Overvoltage tolerant bilateral switch
[2] tPHL and tPLH propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified
capacitance when driven by an ideal voltage source (zero output impedance).
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N where:
fi = input frequency in MHz;
VCC = supply voltage in V;
N = number of inputs.
[4] The condition is VI = GND to 5.5 V.
13. Waveforms
nY or nZ
input
VI
GND
nZ or nY
output
VOH
VOL
VM
t PLH
VM
VM
t PHL
VM
001aaa541
Measurement points are given in Table 11.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 10. Input (Y or Z) to output (Z or Y) propagation delays.
Table 11: Measurement points
Supply voltage Input
VCC
2.3 V to 2.7 V
2.7 V
VM
0.5 × VCC
1.5 V
3.0 V to 3.6 V
1.5 V
4.5 V to 5.5 V
0.5 × VCC
Output
VM
0.5 × VCC
1.5 V
1.5 V
0.5 × VCC
9397 750 13027
Product data sheet
Rev. 01 — 2 April 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 23
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