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PDF SCAN921260 Data sheet ( Hoja de datos )
| Número de pieza | SCAN921260 | |
| Descripción | X6 1:10 Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 2004
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SCAN921260
X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and
at-speed BIST
General Description
The SCAN921260 integrates six deserializer devices into a
single chip. The SCAN921260 can simultaneously deserial-
ize up to six data streams that have been serialized by the
National Semiconductor SCAN921023 Bus LVDS serializer.
The device also includes a seventh serial input channel that
serves as a redundant input.
Each deserializer block in the SCAN921260 operates inde-
pendently with its own clock recovery circuitry and lock-
detect signaling.
The SCAN921260 uses a single +3.3V power supply with an
estimated power dissipation of 1.2W at 3.3V with a PRBS-15
pattern. Refer to the Connection Diagrams for packaging
information.
Features
n IEEE 1149.1 (JTAG) Compliant and at-speed BIST test
modes
n Deserializes one to six BusLVDS input serial data
streams with embedded clocks
n Seven selectable serial inputs to support n+1
redundancy of deserialized streams
n Seventh channel has single pin monitor output that
reflects input from seventh channel input
n Parallel clock rate up to 66MHz
n On chip filtering for PLL
n High impedance inputs upon power off (Vcc = 0V)
n Single power supply at +3.3V
n 196-pin LBGA package (Low-profile Ball Grid Array)
package
n Industrial temperature range operation: −40 to +85
Functional Block Diagram
Typical Application
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS200147
20014702
www.national.com
1 page  
Control Pins Truth Table
PWRDN REN
HH
SEL2
L
SEL1
L
SEL0
L
HHL LH
HH L H L
HH L HH
HHHL L
HHH L H
HHHH L
HHHHH
LXXXX
HLXXX
Rout
Din6 Decoded to
Rout 0 (0:9)(Note
11)
Din6 Decoded to
Rout 1 (0:9)(Note
11)
Din6 Decoded to
Rout 2 (0:9)(Note
11)
Din6 Decoded to
Rout 3 (0:9)(Note
11)
Din6 Decoded to
Rout 4 (0:9)(Note
11)
Din6 Decoded to
Rout 5 (0:9)(Note
11)
Din6 is not
Decoded
Din6 is not
Decoded
Z
Z
CHTST
Din0 (not
decoded)
Din1 (not
decoded)
Din2 (not
decoded)
Din3 (not
decoded)
Din4 (not
decoded)
Din5 (not
decoded)
Z
Din6 (not
decoded)
Z
Z
LOCK[0:5]
Active(Note 9)
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RCLK[0:5]
Active(Notes 10,
11)
Active(Note 9)
Active(Notes 10,
11)
Active(Note 9)
Active(Notes 10,
11)
Active(Note 9)
Active(Notes 10,
11)
Active(Note 9)
Active(Notes 10,
11)
Active(Note 9)
Active(Notes 10,
11)
Active(Note 9)
Active(Note 9)
Z
Active(Note 9)
Active(Notes 10,
11)
Active(Notes 10,
11)
Z
Z
Note 8: The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2].
Note 9: LOCK Active indicates that the LOCK output will reflect the state of it’s respective Deserializer with regard to the selected data stream.
Note 10: RCLK Active indicates that the RCLK will be running if the Deserializer is locked.
Note 11: Rout n[0:9] and RCLK [0:5] are Tri-Stated when LOCKn[0:5] is High.
Timing Diagrams
FIGURE 1. Deserializer Delay tDD
5
20014704
www.national.com
5 Page 
Application Information (Continued)
• Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes.
Surface mount capacitors placed close to power and
ground pins work best. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.001
µF to 0.1 µF. Tantalum capacitors may be in the range 2.2
µF to 10 µF. Voltage rating for tantalum capacitors should
be at least 5X the power supply voltage being used.
Randomly distributed by-pass capacitors should also be
used.
Package and pin layout permitting, it is also recom-
mended to use two vias at each power pin as well as all
RF bypass capacitor terminals. Dual vias reduce the
interconnect inductance between layers by up to half,
thereby reducing interconnect inductance and extending
the effective frequency range of the bypass components.
• Leave unused Bus LVDS receiver inputs open (floating).
• Isolate TTL signals from Bus LVDS signals.
There are more common practices which should be followed
when designing PCBs for BLVDS/LVDS signaling. General
application guidelines are available in the LVDS Owner’s
Manual (www.national.com/lvds). For packaging information
on BGA’s, please see AN-1126.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-
point configurations, through PCB trace, or through twisted
pair cable. In point-to-point configurations, the transmission
media need only be terminated at the receiver end. Please
note that in point-to-point configurations, the potential of
offsetting the ground levels of the Serializer vs. the Deseri-
alizer must be considered. Also, Bus LVDS provides a +/−
1.2V common mode range at the receiver iwnpwuwts..DataSheet4U.com
FAILSAFE BIASING FOR THE SCAN921260
The SCAN921260 has internal failsafe biasing and an im-
proved input threshold sensitivity of +/− 50mV versus +/−
100mV for the DS92LV1210 or DS92LV1212. This allows for
greater differential noise margin in the SCAN921260. How-
ever, in cases where the receiver input is not being actively
driven, the increased sensitivity of the SCAN921260 can
pickup noise as a signal and cause unintentional locking. For
example, this can occur when the input cable is discon-
nected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. The pull-up and pull-down
resistors (R1 and R2) provide a current path through the
termination resistor (RL) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 8 for the Failsafe
Biasing Setup.
The parameter tRNM is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling. After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called tRNM. It is the offset from tDJIT(min or max) for the test
mask within the eye opening.
The vertical limits of the mask are determined by the
SCAN921260 receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 9 for a graphic
representation of tDJIT and tRNM.
20014727
FIGURE 8. Failsafe Biasing Setup
11 www.national.com
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| PDF Descargar | [ Datasheet SCAN921260.PDF ] | |
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