W364M72V-XSBX PDF даташит
Спецификация W364M72V-XSBX изготовлена «White Electronic Designs Corporation» и имеет функцию, называемую «64Mx72 Synchronous DRAM». |
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Детали детали
Номер произв | W364M72V-XSBX |
Описание | 64Mx72 Synchronous DRAM |
Производители | White Electronic Designs Corporation |
логотип |
16 Pages
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White Electronic Designs
W364M72V-XSBX
www.DataSheet4UA.cDoVmANCED*
64Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
3.3V ±0.3V power supply for core and I/Os
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 64M x 72
Weight: W364M72V-XSBX - TBD grams typical
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
BENEFITS
66% SPACE SAVINGS
Reduced part count from 9 to 1
Reduced I/O count
• 55% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 512MByte (4.5Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 9 chips containing
512M bits. Each chip is internally configured as a quad-
bank DRAM with a synchronous interface. Each of the
chip’s 134,217,728-bit banks is organized as 8,192 rows
by 2,048 columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
ACTUAL SIZE
White Electronic Designs
W364M72V-XSBX
25
Area = 800mm2
32
I/O Count = 219 Balls
SAVINGS – Area: 66% – I/O Count: 55%
Discrete Approach
11.9 11.9 11.9 11.9 11.9 11.9 11.9 11.9 11.9
22.3 54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
Area: 9 x 265mm2 = 2,385mm2
January 2005
Rev. 1
I/O Count: 9 x 54 pins = 486 pins
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
No Preview Available ! |
White Electronic Designs
W364M72V-XSBX
www.DataSheet4UA.cDoVmANCED
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select
the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 4.5Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
The 4.5Gb SDRAM is designed to operate at 3.3V. An
auto refresh mode is provided, along with a power-saving,
power-down mode.
January 2005
Rev. 1
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
No Preview Available ! |
White Electronic Designs
FIGURE 1 – PIN CONFIGURATION
W364M72V-XSBX
www.DataSheet4UA.cDoVmANCED
Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A DQ0 DQ14 DQ15 VSS VSS A9 A10 A11 A8 VCCQ VCCQ DQ16 DQ17 DQ31 VSS
B DQ1 DQ2 DQ12 DQ13 VSS VSS A0 A7 A6 A1 VCC VCC DQ18 DQ19 DQ29 DQ30
C DQ3 DQ4 DQ10 DQ11 VCC
VCC
A2
A5
A4
A3 VSS VSS DQ20 DQ21 DQ27 DQ28
D DQ6 DQ5 DQ8 DQ9 VCCQ VCCQ A12 DNU DNU DNU VSS VSS DQ22 DQ23 DQ26 DQ25
E DQ7 DQML0 VCC DQMH0 NC NC NC BA0 BA1 NC NC NC DQML1 VSS NC DQ24
F CAS0# WE0# VCC CLK0 NC
RAS1# WE1# VSS DQMH1 CLK1
G CS0# RAS0# VCC CKE0 NC
CAS1# CS1# VSS NC CKE1
H VSS VSS VCC VCCQ VSS
VCC VSS Vss VCCQ VCC
J VSS VSS VCC VCCQ VSS
VCC VSS VSS VCCQ VCC
K NC CKE3 VCC CS3# NC
NC CKE2 VSS RAS2# CS2#
L NC CLK3 VCC CAS3# RAS3#
NC CLK2 VSS WE2# CAS2#
M DQ56 DQMH3 VCC WE3# DQML3 CKE4 NC CLK4 CAS4# WE4# RAS4# CS4# DQMH2 VSS DQML2 DQ39
N DQ57 DQ58 DQ55 DQ54 NC NC NC NC DQ71 DQ70 DQML4 NC DQ41 DQ40 DQ37 DQ38
P DQ60 DQ59 DQ53 DQ52 VSS VSS NC NC DQ69 DQ68 VCC VCC DQ43 DQ42 DQ36 DQ35
R DQ62 DQ61 DQ51 DQ50 VCC VCC NC NC DQ67 DQ66 VSS VSS DQ45 DQ44 DQ34 DQ33
T Vss DQ63 DQ49 DQ48 VCCQ VCCQ NC
NC DQ65 DQ64 VSS
VSS DQ47 DQ46 DQ32 VCC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
January 2005
Rev. 1
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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W364M72V-XSBX | 64Mx72 Synchronous DRAM | White Electronic Designs Corporation |
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