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GS8162V72CC-150 PDF даташит

Спецификация GS8162V72CC-150 изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «256K x 72 18Mb S/DCD Sync Burst SRAMs».

Детали детали

Номер произв GS8162V72CC-150
Описание 256K x 72 18Mb S/DCD Sync Burst SRAMs
Производители GSI Technology
логотип GSI Technology логотип 

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GS8162V72CC-150 Даташит, Описание, Даташиты
Preliminary
GS8162V72CCw-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/150
209-Bump BGA
Commercial Temp
Industrial Temp
256K x 72
18Mb S/DCD Sync Burst SRAMs
333 MHz150 MHz
1.8 V VDD
1.8 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
• Pb-Free 209-bump BGA package available
Functional Description
Applications
The GS8162V72CC is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS8162V72CC is an SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS8162V72CC operates on a 1.8 V power supply. All input are
1.8 V compatible. Separate output power (VDDQ) pins are used to
decouple output noise from the internal circuits and are 1.8 V
compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tKQ
tCycle
Curr
tKQ
tCycle
Curr
Parameter Synopsis
-333 -300 -250 -200 -150 Unit
2.8 2.8 3.0 3.0 3.8 ns
3.0 3.3 4.0 5.0 6.7 ns
545 495 425 345 270 mA
4.5 5.0 5.5 6.5 7.5 ns
4.5 5.0 5.5 6.5 7.5 ns
380 345 315 275 250 mA
Rev: 1.01 2/2005
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology









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GS8162V72CC-150 Даташит, Описание, Даташиты
Preliminary
GS8162V72CCw-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/150
GS8162V72C Pad Out—209-Bump BGA—Top View (Package C)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
1
DQG
DQG
DQG
DQG
DQPG
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPD
DQD
DQD
DQD
DQD
2
DQG
DQG
DQG
DQG
DQPC
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPH
DQD
DQD
DQD
DQD
3
A
BC
BH
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CK
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
A
TMS
45678
E2
ADSP
ADSC
ADV
E3
BG NC
B
A BB
BD NC E1 NC BE
NC NC G GW NC
VDDQ
VDD
VDD
VDD
VDDQ
VSS VSS ZQ VSS VSS
VDDQ
VDD
MCH
VDD
VDDQ
VSS VSS MCL VSS
VSS
VDDQ
VDD
MCL
VDD
VDDQ
NC VSS MCL VSS NC
VDDQ
VDD
FT
VDD
VDDQ
VSS VSS MCL VSS
VSS
VDDQ
VDD
SCD
VDD
VDDQ
VSS VSS ZZ VSS VSS
VDDQ
VDD
VDD
VDD
VDDQ
NC NC LBO NC NC
AAAAA
A A A1 A A
TDI A A0 A TDO
11 x 19 Bump BGA14 x 22 mm2 Body1 mm Bump Pitch
9
A
BF
BA
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
A
TCK
10
DQB
DQB
DQB
DQB
DQPF
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPA
DQE
DQE
DQE
DQE
11
DQB
DQB
DQB
DQB
DQPB
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPE
DQE
DQE
DQE
DQE
Rev: 1.01 2/2005
2/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology









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GS8162V72CC-150 Даташит, Описание, Даташиты
GS8162V72C BGA Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
Type
I
I
I/O
BA, BB, BC,BD, BE, BF, BG,BH
I
NC
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
SCD
MCH
MCL
BW
I
I
I
I
I
I
I
I
I
I
I
I
I
ZQ I
TMS
TDI
TDO
TCK
VDD
VSS
VDDQ
BPR1999.05.18
I
I
O
I
I
I
I
Preliminary
GS8162V72CCw-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/150
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.01 2/2005
3/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology










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