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ZL50405 PDF даташит

Спецификация ZL50405 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «Managed5-Port 10/100 M Ethernet Switch».

Детали детали

Номер произв ZL50405
Описание Managed5-Port 10/100 M Ethernet Switch
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL50405 Даташит, Описание, Даташиты
ZL50405
Managed5-Port 10/100 M Ethernet Switch
www.DataSheet4U.com
Data Sheet
Features
• Integrated Single-Chip 10/100 Ethernet Switch
• Four 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100 Mbps auto-negotiating port with
MII interface option, that can be used as a
WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
• Embedded 2 Mbits (256 KBytes) internal memory
• supports up to 4 K byte frames
• L2 switching
• MAC address self learning, up to 4 K MAC
addresses using internal table
• Supports IP Multicast with IGMP snooping, up
to 4 K IP Multicast groups
• Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
• Supports Ethernet multicasting and
broadcasting and flooding control
• VLAN Support
• Supports port-based VLAN and tagged-based
January 2005
Ordering Information
ZL50405GDC
208 Pin LBGA
-40°C to +85°C
VLAN (IEEE 802.1Q), up to 4 K VLANs
• Supports both shared VLAN learning (SVL)
and independent VLAN learning (IVL)
• CPU access supports the following interface
options:
• 8/16-bit parallel and Serial+MII interface in
managed mode
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I2C EEPROM
interface
• Failover Features
• Rapid link failure detection using
hardware-generated heartbeat packets
• link failover in less than 50 ms
• Rate Control (both ingress and egress)
• Bandwidth rationing, Bandwidth on demand,
8/16-bit
or
C Serial
P
U
MII
EEPROM I2C
ZL50405
5-Port 10/100M
Ethernet Switch
MII
RMII / MII / GPSI
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL50405 Даташит, Описание, Даташиты
ZL50405
Data Sheet
www.DataSheet4U.com
SLA (Service Level Agreement)
• Smooth out traffic to uplink port
• Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
• Egress Rate Control
• Down to 16 kbps Rate Control granularity
• Per queue traffic shaper on uplink port
• Packet Filtering and Port Security
• Static address filtering for source and/or destination MAC
• Static MAC address not subject to aging
• Secure mode freezes MAC address learning (each port may independently use this mode)
• Supports port authentication (IEEE 802.1x)
• QoS Support
• Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with
strict priority and/or WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds.
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
• Supports per-system option to enable flow control for best effort frames even on QoS enabled ports
• Classification based on:
• Port based priority
• VLAN Priority field in VLAN tagged frame
• DS/TOS field in IP packet
• UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
• The precedence of the above classifications is programmable
• Supports IEEE 802.3ad link aggregation
• Up to 8 trunk groups, with up to 4 ports per group
• Supports load sharing among trunk ports based on:
- Source port
- Source and/or destination MAC address
• Supports module hot swap on all ports
• MIB Statistics counters for all ports
• Full Duplex Ethernet IEEE 802.3x Flow Control
• Backpressure flow control for Half Duplex ports
• Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports
• Built-in reset logic triggered by system malfunction
• Built-In Self Test for internal SRAM
• IEEE-1149.1 (JTAG) test port
2
Zarlink Semiconductor Inc.









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ZL50405 Даташит, Описание, Даташиты
ZL50405
Data Sheet
Description
www.DataSheet4U.com
The ZL50405 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 4 ports at 10/100 Mbps, 1 uplink port at 10/100 Mbps, and a CPU interface for managed, lightly managed
and unmanaged switch applications. The chip supports up to 4 K MAC addresses and up to 4 K tagged-based
Virtual LANs (VLANs).
With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50405 provides
powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission
priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission
priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or
the UDP/TCP logical port fields in IP packets. The ZL50405 recognizes a total of 16 UDP/TCP logical ports, 8
hard-wired and 8 programmable (including one programmable range).
The ZL50405 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure
to the CPU. The CPU can then failover that link to an alternate link.
The ZL50405 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 4 ports. Port
trunking/load sharing can be used to group ports between interlinked switches to increase the effective network
bandwidth.
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50405 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network
management solution.
The ZL50405 is fabricated using 0.18 micron technology. The ZL50405 is packaged in a 208-pin Ball Grid Array
package.
3
Zarlink Semiconductor Inc.










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