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H55S1262EFP-60E PDF даташит

Спецификация H55S1262EFP-60E изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O».

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Номер произв H55S1262EFP-60E
Описание 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H55S1262EFP-60E Даташит, Описание, Даташиты
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128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O
Specification of
128M (8Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 /Aug. 2009
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H55S1262EFP-60E Даташит, Описание, Даташиты
11
128Mbit (8Mx16bit) MobilewwSwD.DRataMSheemet4oUr.cyom
H55S1262EFP Series
Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No.
0.1
0.2
1.0
1.1
1.2
Initial Draft
- Define
IDD specification
History
-. Correct
Temp range(p.9 & p.10)
-. Modify
IDD Values(p.11 & p.12)
-. Omit a typo in a package inforamtion
-. Modify package information(add tolerance)
Draft Date
Sep. 2007
Feb. 2008
Jun. 2008
Jul. 2009
Aug. 2009
Remark
Preliminary
Preliminary
Rev 1.2 /Aug. 2009
2









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H55S1262EFP-60E Даташит, Описание, Даташиты
11
128Mbit (8Mx16bit) MobilewwSwD.DRataMSheemet4oUr.cyom
H55S1262EFP Series
DESCRIPTION
The Hynix H55S1262EFP is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix 128M Mobile SDRAM is 134,217,728-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the
main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of
2,097,152x16.
Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch
each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the
input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/
Output bus. All the commands are latched in synchronization with the rising edge of CLK.
The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8
locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini-
tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed
operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-
access operation.
Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a
burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any
cycle(This pipelined design is not restricted by a 2N rule).
The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,
half array, quarter array Temperature Compensated Self Refresh of 45 or 85 degrees oC.
The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to
reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically
adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power
reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut
off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout
flexibility.
All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
Rev 1.2 /Aug. 2009
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