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PDF NCP5386B Data sheet ( Hoja de datos )
| Número de pieza | NCP5386B | |
| Descripción | 1/2 Phase Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5386, NCP5386A,
NCP5386B
1/2 Phase Controller for
CPU and Chipset
Applications
The NCP5386 is a one− or two−phase buck controller which
combines differential voltage and current sensing, and adaptive
voltage positioning to power both AMD and Intel processors and
chipsets. Dual−edge pulse−width modulation (PWM) combined with
inductor current sensing reduces system cost by providing the fastest
initial response to transient load events. Dual−edge multi−phase
modulation reduces total bulk and ceramic output capacitance
www.DarteaqSuhiereedt4tUo.csoamtisfy transient load−line regulation.
A high performance operational error amplifier is provided, which
allows easy compensation of the system. The proprietary method of
Dynamic Reference Injection (Patented) makes the error amplifier
compensation virtually independent of the system response to VID
changes, eliminating tradeoffs between overshoot and dynamic VID
performance.
Features
• Meets Intel’s VR 10.0 and 11.0, and AMD Specifications
• No load Intel VR Offset of −19 mV (NCP5386), +20 mV
(NCP5386A), and 0 mV (NCP5386B)
• Dual−Edge PWM for Fastest Initial Response to Transient Loading
• High Performance Operational Error Amplifier
• Supports both VR11 and Legacy Soft−Start Modes
• Dynamic Reference Injection (Patent# 7057381)
• DAC Range from 0.5 V to 1.6 V
• "0.5% System Voltage Accuracy from 1.0 V to 1.6 V
• True Differential Remote Voltage Sensing Amplifier
• Phase−to−Phase Current Balancing
• “Lossless” Differential Inductor Current Sensing
• Differential Current Sense Amplifiers for each Phase
• Adaptive Voltage Positioning (AVP)
• Frequency Range: 100 kHz – 1.0 MHz
• OVP with Resettable, 8 Event Delayed Latch
• Threshold Sensitive Enable Pin for VTT Sensing
• Power Good Output with Internal Delays
• Programmable Soft−Start Time
• This is a Pb−Free Device*
Applications
• Desktop Processors and Chipsets
• Server Processors and Chipsets
• DDR
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
http://onsemi.com
1 32
QFN32, 5 x 5*
MN SUFFIX
CASE 485AF
MARKING
DIAGRAMS
1
NCP5386x
AWLYYWWG
*Pin 33 is the thermal pad on the bottom of the device.
NCP5386 = Specific Device Code
x = Blank, A or B
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP5386MNR2G*
QFN32
(Pb−Free)
2500 /
Tape & Reel
NCP5386AMNR2G* QFN32
(Pb−Free)
2500 /
Tape & Reel
NCP5386BMNR2G* QFN32
(Pb−Free)
2500 /
Tape & Reel
*Temperature Range: 0°C to 85°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2008
May, 2008 − Rev. 1
1
Publication Order Number:
NCP5386/D
1 page  
NCP5386, NCP5386A, NCP5386B
DACMODE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
SS
VR10/11/AMD
DAC
DAC
NCP5386/A/B
+
-
VS−
VS+
DIFFOUT
www.DataSheet4U.com
1.3 V
VFB
COMP
VDRP
CS1
CS1N
CS2
CS2N
-
+
Diff Amp
+
-
Error Amp
Droop
Amplifier
+−
1.3 V
+
-
Gain = 6
+
-
Gain = 6
Fault
+
-
+
-
NTC
VR_FAN
NTC
GND
ENB G1
ENB G2
ROSC
ILIM
EN
VCC
12VMON
Oscillator
+
-
VCC UVLO
OVER
DIFFOUT
Fault
+
- ILimit
Fault Logic
3 Phase
Detect
and
Monitor
Circuits
+
-
12VMON UVLO
Figure 4. Simplified Block Diagram
http://onsemi.com
5
DRVON
VR_RDY
5 Page 
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF)
Parameter
Test Conditions
Min
Overvoltage Protection
Overvoltage Threshold
DAC+
160
Delay (Note 3)
−
Undervoltage Protection
VCC UVLO Start Threshold
VCC UVLO Stop Threshold
VCC UVLO Hysteresis
VID Inputs
4
3.8
100
Upper Threshold
www.DataLSohweeer tT4hUr.ecsohmold
Input Bias Current
VUPPER
VLOWER
−
300
−
Delay before Latching VID Change
(VID De−Skewing) (Note 3)
Measured from the edge of the first VID
change
500
Internal DAC Slew Rate Limiter
Positive Slew Rate Limit
Negative Slew Rate Limit
Input Supply Current
VID Step of +500 mV
VID Step of −500 mV
−
−
VCC Operating Current
Temperature Sensing
EN = LOW, No PWM
−
VR_FAN Upper Voltage Threshold
Fraction of VREF voltage above which
VR_FAN output pulls low
−
VR_FAN Lower Voltage Threshold
Fraction of VREF voltage below which
VR_FAN output is open
−
VR_FAN Output Saturation Voltage
VR_FAN Output Leakage Current
ISINK = 4 mA
High Impedance State
−
−
NTC Pin Bias Current
−
12VMON
12VMON (Rising Threshold)
Sufficient power stage supply voltage
0.728
12VMON (Falling Threshold)
Insufficient power stage supply voltage
0.643
3. Guaranteed by design. Not tested in production.
Typ
−
100
−
−
215
−
−
−
−
6.3
−6.3
−
0.4 x
VREF
0.33 x
VREF
−
−
−
−
−
Max
DAC+
200
−
4.5
4.3
−
800
−
500
800
−
−
20
−
−
0.3
1
1
0.821
0.725
Units
mV
ns
V
V
mV
mV
mV
nA
ns
mV/ms
mV/ms
mA
−
−
V
mA
mA
V
V
http://onsemi.com
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NCP5386B.PDF ] | |
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