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PDF HMD2564Z1 Data sheet ( Hoja de datos )
| Número de pieza | HMD2564Z1 | |
| Descripción | 1Mbit(256x4bit) Fast Page Mode | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMD2564Z1
1Mbit(256x4bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design
Part No. HMD2564Z1
DESCRIPTION
The HMD2564Z1 is an 256K x 4 bits Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of
memory cells
within the same row. Power supply voltage (+5V ), access time (-5, -6), power consumption(Normal or Low power), and package
type (ZIP) are optional features of this Module. The HMD2564Z1 have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities.
The HMD2564Z1 is optimized for application to the systems, which are required high density and large capacity such as main
memory for main frames and mini computers, personal computer and high performance microprocessor systems.
www.DataSheet4U.com
The HMD2564Z1 provides common data and outputs.
Features
w Fast Page Mode operation
w CAS-before-RAS refresh capability
w RAS-only and Hidden refresh capability
w Fast parallel test mode capability
w TTL(5V) compatible inputs and outputs
w Early write or output enable controlled write
w Available in 20pin ZIP packages
w Single +5V± 10% power supply
w 1,024 Refresh Cycles/16ms
w Performance Range
Speed
HMD2564Z1-5
HMD2564Z1-6
tRAC
50
60
tCAC
15
15
tRC
90
110
tPC
35
40
PIN DESCRIPTION
PIN
A0 – A9
FUNCTION
Address Inputs
PIN FUNCTION
/WE
Read/Write
Enable
DQ0 –
DQ3
Data
Input/Output
Vcc
Power
(+5V)
/RAS
Row Address
Strobe
Vss
Ground
/CAS
Column
Address Strobe
NC
No
Connection
Data Output
/OE Enable
PIN ASSIGNMENT
PIN SYMBOL
1 /OE
2 /CAS
3 DQ2
4 DQ3
5 VSS
6 DQ0
7 DQ1
8 /WE
9 /RAS
10 NC
11 A0
12 A1
13 A2
14 A3
15 VCC
16 A4
17 A5
18 A6
19 A7
20 A8
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD2564Z1
4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only,
if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD <= tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH /
VOL .
7. TWCS, TRWD, TCWD, TCPWD are non restrictive operating parameter. They are included in the data sheet as electrical
characteristics
only. If twcs >= twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout
the entire cycle. If tCWD >= tCWD (min), tRWD >= tRWD (min), TCPWD>= TCPWD(min), then the cycle is a read-modify-write
www.DataSheet4U.ccyocmle and the data output will contain the data read from the selected address. If neither of the above conditions is
satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycles.
9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled
write cycle and read-modify-write cycles.
10. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only,
if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
11. tASC, tCAH are are referenced to the earlier /CAS falling edge.
12. tCP is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle.
13. tCWD is referenced to the later /CAS falling edge at word read-modify-write cycle.
14. tCWL is specified from /WE falling edge to the earlier /CAS rising edge .
15. tCSR is referenced to the earlier /CAS falling edge before /RAS transition low.
16. tCHR is referenced to the later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
5
HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HMD2564Z1.PDF ] | |
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