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PDF HMD4M32M8EAG Data sheet ( Hoja de datos )
| Número de pieza | HMD4M32M8EAG | |
| Descripción | 16Mbyte(4Mx32) 72-pin EDO MODE | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMD4M32M8EG/8EAG
16Mbyte(4Mx32) 72-pin EDO MODE, 2K/4K Ref. SIMM Design 5V
Part No. HMD4M32M8EG, HMD4M32M8EAG
GENERAL DESCRIPTION
The HMD4M32M8E is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of eight CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD4M32M8EG-- 2048 Cycles/32ms Ref. Gold
HMD4M32M8EAG-- 4096 Cycles/64ms Ref. Gold
w Access times : 50, 60ns
w High-density 16MByte design.
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w EDO(extended data out) mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
MARKING
-5
-6
M
PRESENCE DETECT PINS
Pin 50ns 60ns
PD1
Vss
Vss
PD2
NC
NC
PD3
Vss
NC
PD4
Vss
NC
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 25 DQ22 49 DQ8
2
DQ0
26
DQ7
50 DQ24
3 DQ16 27 DQ23 51
DQ9
4
DQ1
28
A7
52 DQ25
5 DQ17 29 A11 53 DQ10
6
DQ2
30
Vcc
54 DQ26
7 DQ18 31 A8 55 DQ11
8
DQ3
32
A9
56 DQ27
9 DQ19 33 NC 57 DQ12
10 Vcc 34 /RAS2 58 DQ28
11 NC 35 NC 59 Vcc
12 A0 36 NC 60 DQ29
13 A1 37 NC 61 DQ13
14 A2 38 NC 62 DQ30
15 A3 39 Vss 63 DQ14
16 A4 40 /CAS0 64 DQ31
17 A5 41 /CAS2 65 DQ15
18 A6 42 /CAS3 66 NC
19 A10 43 /CAS1 67
20 DQ4 44 /RAS0 68
Vss
PD2
21 DQ20 45 NC 69 PD3
22 DQ5 46 NC 70 PD4
23 DQ21 47
/WE
71
NC
24 DQ6 48 NC 72 Vss
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
5
50ns
13ns
90ns
6
60ns
15ns
110ns
tHPC
26ns
30ns
A0-A11:Address Input (4K Ref.)
A0-A10:Address Input (2K Ref.)
*Note: A11 is used for only HMD4M32M8EAG
URL:www.hbe.co.kr
REV. 1.0(August. 2002)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD4M32M8EG/8EAG
Column address hold time
tCAH
8
10
ns
Column address hold referenced to /RAS
tAR 40
45
ns
Column Address to /RAS lead time
tRAL 25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
40
45
ns
Write command pulse width
tWP 10
10
ns
Write command to /RAS lead time
www.DataSheWetr4itUe.ccoommmand to /CAS lead time
tRWL
tCWL
13
8
15
10
ns
ns
Data-in set-up time
tDS 0
0
ns
Data-in hold time
tDH 8
10
ns
Data-in hold referenced to /RAS
tDHR
40
45
ns
Refresh period
tREF 32 32 ns
Write command set-up time
tWCS
0
0
ns
/CAS to /W delay time
tCWD
36
40
ns
/RAS to /W delay time
tRWD
73
85
ns
/CAS precharge(C-B-R counter test)
tCPT 20
20
ns
Column address to /W delay time
tAWD
48
55
ns
Access time from /CAS precharge
tCPA 30 35 ns
/CAS precharge time (Hyper Page cycle)
tCP 8
10
ns
/RAS pulse width (Hyper Page cycle)
tRASP
50
200K 60
200K
ns
/WE to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/WE to /RAS hold time (C-B-R refresh)
NOTES
tWRH
10
10
ns
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbe.co.kr
REV. 1.0(August. 2002)
5 HANBit Electronics Co.,Ltd.
5 Page | ||
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