HMD8M32F4E Datasheet PDF - Hanbit Electronics
| Part Number | HMD8M32F4E | |
| Description | 32Mbyte(8Mx32) EDO Mode | |
| Manufacturers | Hanbit Electronics | |
| Logo |  |
|
|
There is a preview and HMD8M32F4E download ( pdf file ) link at the bottom of this page. Total 6 Pages | ||
Preview 1 page No Preview Available !
HANBit
HMD8M32F4E
32Mbyte(8Mx32) EDO Mode 4K Ref. 100Pin SMM, 5V Design
Part No. HMD8M32F4E
GENERAL DESCRIPTION
The HMD8M32F4E is a 8M x 32bit dynamic RAM high density memory module. The module consists of four CMOS
4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 100-pin, double-sided, FR-4-printed circuit board. A 0.1uF
or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components.
The module is a single In-line memory module with edge connections and is intended for mounting in to 100-pin edge
connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and
outputs are TTL-compatible.
FEATURES
www.DataSheet4U.com
w Access times : 50, 60ns
w High-density 32MByte design
w Single +5V ± 0.5V power supply
w JEDEC Standard pinout
w EDO mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
60ns access
w Packages
100-pin SMM
-5
-6
F
PERFORMANCE RANGE
Speed
5
tRAC
50ns
6 60ns
tCAC
13ns
15ns
tRC
90ns
110ns
tHPC
26ns
30ns
PIN ASSIGNMENT
P1 P2
PIN Symbol PIN Symbol PIN Symbol PIN Symbol
1 Vcc 26 Vcc 51 Vcc 76 Vcc
2 NC 27 /CAS0 52 NC 77 /CAS2
3 /RAS0 28 /CAS1 53 /RAS2 78 /CAS3
4 /RAS1 29
NC
54 /RAS3 79 DQ22
5 DQ15 30
NC
55 DQ31 80 DQ21
6 DQ14 31
NC
56 DQ30 81 DQ20
7 DQ13 32
NC
57 DQ29 82 DQ19
8 Vss 33 Vss 58 Vss 83 Vss
9 DQ12 34
NC
59
NC
84 DQ18
10 DQ11 35
NC
60
/WE 85 DQ17
11 DQ10 36
DQ9
61
NC
86 DQ16
12 DQ8 37 DQ7 62 NC 87 NC
13 Vss 38 Vss 63 Vss 88 Vss
14 DQ6 39 DQ5 64 NC 89 NC
15 DQ4 40
NC
65
NC
90
NC
16 DQ3 41 A11
66 DQ28 91
NC
17 DQ2 42 A10
67 DQ27 92
NC
18 Vss 43 Vss 68 Vss 93 Vss
19 DQ1 44 A9 69 DQ26 94 NC
20 DQ0 45
A8
70 DQ25 95
Vss
21 A0 46 A7 71 DQ24 96 NC
22 A1 47 A6 72 DQ23 97 NC
23 A2 48 A5 73 Vss 98 Vss
24 A3 49 A4 74 NC 99 NC
25 Vcc 50 Vcc 75 Vcc 100 Vcc
100PIN SMM
TOP VIEW
HANBit Electronics Co.,Ltd.
|
| |
 
HANBit
HMD8M32F4E
Column address hold time
tCAH
8
10
ns
Column Address to /RAS lead time
tRAL 25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
50
55
ns
Write command pulse width
tWP 10
10
ns
Write command to /RAS lead time
tRWL
13
10
ns
Write command to /CAS lead time
tCWL
8
10
ns
www.DataSheet4U.com Data-in set-up time
tDS 0
0
ns
Data-in hold time
tDH 8
10
ns
Refresh period
tREF
64 64 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA
30 35 ns
/CAS precharge time (Fast page)
tCP 8
10
ns
/RAS pulse width (Fast page )
tRASP
50 200K 60 200K
ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1. An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh
cycles before proper device operation is achieved.
2. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1TTL loads and 100pF
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point
only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to
VOH or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
HANBit Electronics Co.,Ltd.
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for HMD8M32F4E electronic component. |
| Information | Total 6 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ HMD8M32F4E.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| HMD8M32F4E | The function is 32Mbyte(8Mx32) EDO Mode. Hanbit Electronics | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
HMD8
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||