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PDF HMD8M32M16EG Data sheet ( Hoja de datos )
| Número de pieza | HMD8M32M16EG | |
| Descripción | 32Mbyte(8Mx32) 72-pin EDO MODE | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD8M32M16EG
32Mbyte(8Mx32) 72-pin EDO MODE 2K Ref. SIMM Design 5V
Part No. HMD8M32M16EG
GENERAL DESCRIPTION
The HMD8M32M16EG is a 8M x 32bit dynamic RAM high density memory module. The module consists of sixteen
CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1
or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a
single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD8M32M16EG- 2048 Cycles/32ms Ref. Gold
w Access times : 50, 60ns
w High-density 32MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard PDpin and pinout
w EDO mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
MARKING
-5
-6
M
PRESENCE DETECT PINS
Pin 50ns
PD1
NC
PD2
Vss
PD3
Vss
PD4
Vss
PERFORMANCE RANGE
Speed
tRAC
tCAC
5
50ns
13ns
6
60ns
15ns
60ns
NC
Vss
NC
NC
tRC
90ns
110ns
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 25 DQ22 49 DQ8
2
DQ0
26
DQ7
50 DQ24
3 DQ16 27 DQ23 51
DQ9
4
DQ1
28
A7
52 DQ25
5 DQ17 29 NC 53 DQ10
6
DQ2
30
Vcc
54 DQ26
7 DQ18 31 A8 55 DQ11
8
DQ3
32
A9
56 DQ27
9 DQ19 33 NC 57 DQ12
10 Vcc 34 NC 58 DQ28
11 NC 35 NC 59 Vcc
12 A0 36 NC 60 DQ29
13 A1 37 NC 61 DQ13
14 A2 38 NC 62 DQ30
15 A3 39 Vss 63 DQ14
16 A4 40 /CAS0 64 DQ31
17 A5 41 /CAS2 65 DQ15
18 A6 42 /CAS3 66 NC
19 A10 43 /CAS1 67 PD1
20 DQ4 44 /RAS0 68
PD2
21 DQ20 45 /RAS1 69
PD3
22
23
24
tHPC
26ns
DQ5
46
NC
70 PD4
DQ21 47 /WE 71 NC
DQ6
48 NC
SIMM
72 Vss
TOP VIEW
Note: A11 is not used for HMD8M32M16EG
30ns
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-1-
HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD8M32M16EG
Column address hold time
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
Write command hold referenced to /RAS
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
www.DataSheDeat4taU-.icnosmet-up time
Data-in hold time
Refresh period
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time (C-B-R
refresh)
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWCR
tWP
tRWL
tCWL
tDS
tDH
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
tCP
tRASP
tWRP
8
25
0
0
0
10
50
10
13
8
0
8
0
5
10
5
8
50
10
32
30
200K
10
30
0
0
0
10
55
10
10
10
0
10
0
5
10
5
10
60
10
32
35
200K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-5-
HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HMD8M32M16EG.PDF ] | |
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