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PDF HMD8M36M18G Data sheet ( Hoja de datos )
| Número de pieza | HMD8M36M18G | |
| Descripción | 32Mbyte(8Mx36) 72-pin FP | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMD8M36M18G
32Mbyte(8Mx36) 72-pin FP with Parity MODE 2K Ref. SIMM Design 5V
Part No. HMD8M36M18, HMD8M36M18G
GENERAL DESCRIPTION
The HMD8M36M18G is a 8M x 36bit dynamic RAM high density memory module. The module consists of sixteen
CMOS 4M x 4bit DRAM in 24-pin SOJ packages and two CMOS 4Mx 4bit Quad-CAS DRAM in 28pin SOJ packages
mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections
and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single
5V DC power supply and all inputs and outputs are TTL-compatible.
www.DataSheet4U.com
FEATURES
w Part Identification
HMD8M36M18---- 2048 Cycles/32ms Ref. Solder Lead
HMD8M36M18G-- 2048 Cycles/32ms Ref. Gold Lead
w Access times : 50, 60ns
w High-density 32MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard PDpin and pinout
w Fast Page with Parity mode operation
w /CAS-before-/RAS refresh capability
w/RAS-only and Hidden refresh capability
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
-5
60ns access
-6
w Packages
72-pin SIMM
M
PRESENCE DETECT PINS(Optional)
PIN ASSIGNMENT
PIN SYMBOL
PIN
SYMBOL
PIN
SYMBO
L
PIN
SYMBOL
1 Vss 19 A10 37 DQ17 55 DQ12
2 DQ0 20 DQ4 38 DQ35 56 DQ30
3 DQ18 21 DQ22 39 Vss 57 DQ13
4 DQ1 22 DQ5 40 /CAS0 58 DQ31
5 DQ19 23 DQ23 41 /CAS2 59 Vcc
6 DQ2 24 DQ6 42 /CAS3 60 DQ32
7 DQ20 25 DQ24 43 /CAS1 61 DQ14
8 DQ3 26 DQ7 44 /RAS0 62 DQ33
9 DQ21 27 DQ25 45 /RAS1 63 DQ15
10 Vcc 28 A7 46 NC 64 DQ34
11 NC 29 NC 47 /WE 65 DQ16
12 A0 30 Vcc 48 NC 66 NC
13 A1 31 A8 49 DQ9 67 PD1
14 A2 32 A9 50 DQ27 68 PD2
15 A3 33 NC 51 DQ10 69 PD3
16 A4 34 NC 52 DQ28 70 PD4
17 A5 35 DQ26 53 DQ11 71 NC
18 A6 36 DQ8 54 DQ29 72 Vss
Pin
PD1
PD2
50ns
NC
Vss
60ns
NC
Vss
SIMM
TOP VIEW
PD3
Vss
NC
PD4
Vss
PERFORMANCE RANGE
NC
Note: A11 is used for only 4K Ref.
Speed
5
6
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
90ns
110ns
URL:www.hbeoc.kr
REV.1.0 (August.2002)
-1-
HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD8M36M18G
Column address set-up time
tASC
0
0
ns
Column address hold time
tCAH
10
10
ns
Column Address to /RAS lead time
tRAL 25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
50
55
ns
Write command pulse width
tWP 10
10
ns
Write command to /RAS lead time
www.DataSheWetr4itUe.ccoommmand to /CAS lead time
tRWL
tCWL
13
13
15
15
ns
ns
Data-in set-up time
tDS 0
0
ns
Data-in hold time
tDH 10
15
ns
Refresh period
tREF 64
64 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA
30
35 ns
/CAS precharge time (Fast page)
tCP 10
10
ns
/RAS pulse width (Fast page )
tRASP
50
200K
60
200K
ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbeoc.kr
REV.1.0 (August.2002)
-5-
HANBit Electronics Co.,Ltd.
5 Page | ||
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| PDF Descargar | [ Datasheet HMD8M36M18G.PDF ] | |
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