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PDF NTD4804N Data sheet ( Hoja de datos )

Número de pieza NTD4804N
Descripción Power MOSFET ( Transistor )
Fabricantes ON Semiconductor 
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NTD4804N
Power MOSFET
30 V, 117 A, Single N−Channel, DPAK/IPAK
Features
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
Applications
CPU Power Delivery
DC−DC Converters
Low Side Switching
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MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (RqJA) (Note 1)
Power Dissipation
(RqJA) (Note 1)
Continuous Drain
Current (RqJA) (Note 2)
Power Dissipation
(RqJA) (Note 2)
Continuous Drain
Current (RqJC)
(Note 1)
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
VDSS
VGS
ID
PD
ID
PD
ID
30
"20
19
15
2.5
14.5
11
1.43
117
91
V
V
A
W
A
W
A
Power Dissipation
(RqJC) (Note 1)
TC = 25°C
Pulsed Drain Current tp=10ms TA = 25°C
Current Limited by Package
TA = 25°C
Operating Junction and Storage Temperature
PD
IDM
IDmaxPkg
TJ, Tstg
93.75
230
45
−55 to
175
W
A
A
°C
Source Current (Body Diode)
Drain to Source dV/dt
IS
dV/dt
78 A
6.0 V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 30 V, VGS = 10 V,
L = 1.0 mH, IL(pk) = 30 A, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8from case for 10 s)
EAS 450 mJ
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
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V(BR)DSS
30 V
RDS(on) MAX
4.0 mW @ 10 V
5.5 mW @ 4.5 V
D
ID MAX
117 A
N−Channel
G
S
4
4
4
12
3
CASE 369C
DPAK
(Bend Lead)
STYLE 2
1 23
1
2
3
CASE 369AC CASE 369D
3 IPAK
DPAK
(Straight Lead) (Straight Lead)
STYLE 2
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
Y = Year
WW = Work Week
4804N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 0
1
Publication Order Number:
NTD4804N/D

1 page




NTD4804N pdf
NTD4804N
TYPICAL PERFORMANCE CURVES
6000
5000
Ciss
TJ = 25°C
4000
3000
Crss
2000
Ciss
1000
Coss
0 VDS = 0 V VGS = 0 V
Crss
15 10 5 0 5 10 15 20 25 30
www.DataSheet4U.com VGS
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
5
4 Q1
3
QT
Q2
2
1
ID = 30 A
TJ = 25°C
0
0 5 10 15 20 25 30
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
1000
VDD = 15 V
ID = 30 A
VGS = 11.5 V
100 tr
td(off)
tf
td(on)
10
30
VGS = 0 V
25 TJ = 25°C
20
15
10
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
5
0
0 0.2 0.4 0.6 0.8 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
1000
10 ms
100
100 ms
10
1
0.1
VGS = 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1 ms
10 ms
dc
1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
500
ID = 30 A
400
300
200
100
0
25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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