74LVC2G240 PDF даташит
Спецификация 74LVC2G240 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Dual inverting buffer/line driver». |
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Детали детали
Номер произв | 74LVC2G240 |
Описание | Dual inverting buffer/line driver |
Производители | NXP Semiconductors |
логотип |
16 Pages
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74LVC2G240
Dual inverting buffer/line driver; 3-state
Rev. 04 — 29 February 2008
www.DataSheet4U.com
Product data sheet
1. General description
The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state
outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at
pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger
action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
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NXP Semiconductors
74LVC2G240
www.DataSheet4U.com
Dual inverting buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2G240DP −40 °C to +125 °C TSSOP8
74LVC2G240DC −40 °C to +125 °C VSSOP8
74LVC2G240GT −40 °C to +125 °C XSON8
74LVC2G240GM −40 °C to +125 °C XQFN8U
Description
Version
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking codes
Type number
74LVC2G240DP
74LVC2G240DC
74LVC2G240GT
74LVC2G240GM
5. Functional diagram
Marking code
V240
V40
V40
V40
EN
1OE
1A
2OE
2A
Fig 1. Logic symbol
1Y
2Y
001aah782
EN
001aah783
Fig 2. IEC logic symbol
74LVC2G240_4
Product data sheet
Rev. 04 — 29 February 2008
© NXP B.V. 2008. All rights reserved.
2 of 16
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74LVC2G240
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Dual inverting buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74LVC2G240
1OE 1
1A 2
2Y 3
GND 4
8 VCC
7 2OE
6 1Y
5 2A
001aaf075
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74LVC2G240
1OE 1
8 VCC
terminal 1
index area
74LVC2G240
2OE 1
7 1OE
1A 2
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aaf076
Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
1Y 2
6 1A
2A 3
5 2Y
001aaf077
Transparent top view
Fig 5. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
1OE
1A
2Y
GND
2A
1Y
2OE
VCC
Pin description
Pin
SOT505-2, SOT765-1, SOT902-1
SOT833-1
17
26
35
44
53
62
71
88
Description
output enable input 1OE (active LOW)
data input
data output
ground (0 V)
data input
data output
output enable input 2OE (active LOW)
supply voltage
74LVC2G240_4
Product data sheet
Rev. 04 — 29 February 2008
© NXP B.V. 2008. All rights reserved.
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Номер в каталоге | Описание | Производители |
74LVC2G240 | Dual inverting buffer/line driver | NXP Semiconductors |
74LVC2G241 | Dual buffer/line driver | NXP Semiconductors |
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