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74LVC2G241 PDF даташит

Спецификация 74LVC2G241 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Dual buffer/line driver».

Детали детали

Номер произв 74LVC2G241
Описание Dual buffer/line driver
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC2G241 Даташит, Описание, Даташиты
74LVC2G241
Dual buffer/line driver; 3-state
Rev. 07 — 5 October 2007
www.DataSheet4U.com
Product data sheet
1. General description
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs 1OE and 2OE:
A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.
A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from 40 °C to +85 °C and 40 °C to +125 °C









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74LVC2G241 Даташит, Описание, Даташиты
NXP Semiconductors
74LVC2G241
www.DataSheet4U.com
Dual buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2G241DP 40 °C to +125 °C TSSOP8
74LVC2G241DC 40 °C to +125 °C VSSOP8
74LVC2G241GT 40 °C to +125 °C XSON8
74LVC2G241GM 40 °C to +125 °C XQFN8
Description
Version
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking
Type number
74LVC2G241DP
74LVC2G241DC
74LVC2G241GT
74LVC2G241GM
5. Functional diagram
Marking code
V241
V41
V41
V41
1 1OE
2 1A
7 2OE
5 2A
1Y 6
2Y 3
Fig 1. Logic symbol
001aaa409
2
1
1
EN1
5
7
2
EN2
6
3
001aaa408
Fig 2. IEC logic symbol
74LVC2G241_7
Product data sheet
Rev. 07 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
2 of 17









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74LVC2G241 Даташит, Описание, Даташиты
NXP Semiconductors
6. Pinning information
6.1 Pinning
74LVC2G241
1OE 1
1A 2
2Y 3
GND 4
8 VCC
7 2OE
6 1Y
5 2A
001aab569
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74LVC2G241
www.DataSheet4U.com
Dual buffer/line driver; 3-state
74LVC2G241
1OE 1
8 VCC
terminal 1
index area
74LVC2G241
2OE 1
7 1OE
1A 2
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aab570
Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
1Y 2
6 1A
2A 3
5 2Y
001aaf057
Transparent top view
Fig 5. Pin configuration SOT902-1 (XQFN8)
6.2 Pin description
Table 3.
Symbol
1OE
1A
2Y
GND
2A
1Y
2OE
VCC
Pin description
Pin
SOT505-2, SOT765-1,
SOT833-1
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
Description
output enable input 1OE (active LOW)
data input
data output
ground (0 V)
data input
data output
output enable input 2OE (active HIGH)
supply voltage
74LVC2G241_7
Product data sheet
Rev. 07 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
3 of 17










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74LVC2G241Dual buffer/line driverNXP Semiconductors
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