74LVC2G74 PDF даташит
Спецификация 74LVC2G74 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Single D-type flip-flop». |
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Детали детали
Номер произв | 74LVC2G74 |
Описание | Single D-type flip-flop |
Производители | NXP Semiconductors |
логотип |
21 Pages
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74LVC2G74
www.DataSheet4U.com
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 06 — 23 December 2009
Product data sheet
1. General description
The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant inputs for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ±24 mA output drive (VCC = 3.0 V)
I ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
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74LVC2G74
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Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name Description
Version
74LVC2G74DP
−40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
74LVC2G74DC
−40 °C to +125 °C
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
74LVC2G74GT
−40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
74LVC2G74GF
−40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
SOT1089
74LVC2G74GD
−40 °C to +125 °C
XSON8U plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
74LVC2G74GM −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking codes
Type number
74LVC2G74DP
74LVC2G74DC
74LVC2G74GT
74LVC2G74GF
74LVC2G74GD
74LVC2G74GM
Marking code[1]
V74
V74
V74
Y4
V74
V74
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
SD
DD
Q
Q
CP CP
FF
Q
Q
RD
RD 001aah725
Fig 1. Logic symbol
S
C1
1D
R
001aah726
Fig 2. IEC logic symbol
74LVC2G74_6
Product data sheet
Rev. 06 — 23 December 2009
© NXP B.V. 2009. All rights reserved.
2 of 21
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74LVC2G74
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Single D-type flip-flop with set and reset; positive edge trigger
C
D
C
RD
SD
CP
Fig 3. Logic diagram
C
C
6. Pinning information
6.1 Pinning
C
C
74LVC2G74
CP 1
D2
Q3
GND 4
8 VCC
7 SD
6 RD
5Q
001aaf642
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
C
C
C
C
mna421
Q
Q
74LVC2G74
CP 1
8 VCC
D2
7 SD
Q3
6 RD
GND 4
5Q
001aaf643
Transparent top view
Fig 5. Pin configuration SOT833-1 and SOT1089
(XSON8)
74LVC2G74_6
Product data sheet
Rev. 06 — 23 December 2009
© NXP B.V. 2009. All rights reserved.
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