74LVCH2T45 PDF даташит
Спецификация 74LVCH2T45 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Dual supply translating transceiver». |
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Детали детали
Номер произв | 74LVCH2T45 |
Описание | Dual supply translating transceiver |
Производители | NXP Semiconductors |
логотип |
30 Pages
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74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
www.DataSheet4U.com
Rev. 03 — 19 January 2010
Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A)
and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and
pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114E Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
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NXP Semiconductors
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
www.DataSheet4U.com
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
±24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16 μA maximum ICC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2T45DC
−40 °C to +125 °C VSSOP8
74LVCH2T45DC
74LVC2T45GT
−40 °C to +125 °C XSON8
74LVCH2T45GT
74LVC2T45GD
−40 °C to +125 °C XSON8U
74LVCH2T45GD
74LVC2T45GM
−40 °C to +125 °C XQFN8U
74LVCH2T45GM
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking
Type number
74LVC2T45DC
74LVCH2T45DC
74LVC2T45GT
74LVCH2T45GT
74LVC2T45GD
74LVCH2T45GD
74LVC2T45GM
74LVCH2T45GM
Marking code
V45
X45
V45
X45
V45
X45
V45
X45
74LVC_LVCH2T45_3
Product data sheet
Rev. 03 — 19 January 2010
© NXP B.V. 2010. All rights reserved.
2 of 32
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NXP Semiconductors
5. Functional diagram
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
www.DataSheet4U.com
5
DIR
2
1A
3
2A
VCC(A)
Fig 1. Logic symbol
7 1B
VCC(B)
6 2B
001aag577
6. Pinning information
6.1 Pinning
74LVC2T45
74LVCH2T45
VCC(A) 1
1A 2
2A 3
GND 4
8 VCC(B)
7 1B
6 2B
5 DIR
001aai904
Fig 3. Pin configuration SOT765-1 (VSSOP8)
DIR
1A
2A
VCC(A)
Fig 2. Logic diagram
1B
2B
VCC(B)
001aag578
74LVC2T45
74LVCH2T45
VCC(A) 1
8 VCC(B)
1A 2
7 1B
2A 3
6 2B
GND 4
5 DIR
001aai905
Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
74LVC_LVCH2T45_3
Product data sheet
Rev. 03 — 19 January 2010
© NXP B.V. 2010. All rights reserved.
3 of 32
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