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What is ZL50411?

This electronic component, produced by the manufacturer "Zarlink Semiconductor", performs the same function as "Managed 9FE Layer-2 Ethernet Switch".


ZL50411 Datasheet PDF - Zarlink Semiconductor

Part Number ZL50411
Description Managed 9FE Layer-2 Ethernet Switch
Manufacturers Zarlink Semiconductor 
Logo Zarlink Semiconductor Logo 


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ZL50411
Managed 9FE Layer-2 Ethernet Switch
www.DataSheet4U.com
Data Sheet
Zarlink Features
• Integrated Single-Chip 10/100 Mbps Ethernet
Switch
• Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100 Mbps auto-negotiating port with
MII interface option, that can be used as a
WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
• Embedded 2.0 Mbits (256 KBytes) internal
memory for control databases and frame data
buffer
• Supports jumbo frames up to 4 KBytes
• CPU access supports the following interface
options:
• 8/16-bit ISA interface
• Serial interface with MII port; recommended
for light management
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I2C EEPROM
interface
• Ethernet IEEE 802.3x flow control for full duplex
ports, back pressure flow control for half duplex
ports
April 2006
Ordering Information
ZL50411GDG 208-Ball LBGA
ZL50411GDG2 208-Ball LBGA**
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Built-in reset logic triggered by system
malfunction
• Built-In Self Test for internal SRAM
• IEEE-1149.1 (JTAG) test port
L2 Switching
• L2 switching
• MAC address self learning, up to 4 K MAC
addresses
• MAC address table supports unicast and
multicast MAC address and IP multicast
address learning
• Supports IP Multicast with IGMP snooping, up to
4 K IP Multicast groups
8/16-bit
or
C Serial
P
U
MII
I2C
EEPROM
ZL50411
9-Port 10/100M
Ethernet Switch
RMII / MII / GPSI
MII 10/100
PHY
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.

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ZL50411 equivalent
ZL50411
Data Sheet
January 2005
www.DataSheet4U.com
• Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
June 2005
• Corrected ordering code to ZL50411GD”G
• Clarified that port mirroring is only available if the source & destination ports are in RMII mode
• Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F
• Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap
TSTOUT[0]
• Added power sequencing recommendation (1.7, “Power Sequencing“ on page 25)
• Added Reverse MII/GPSI timing characteristics (13.4.10, “Reverse General Purpose Serial Interface
(RvGPSI)“ on page 139 and 13.4.11, “MII Management Data Interface (MDIO/MDC)“ on page 140)
• Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50411 (11.0, “Hardware Statistics
Counters“ on page 53)
December 2005
• Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,
“Ball Signal Descriptions“ on page 14)
• Added more text to section 2.8, “JTAG“ on page 28
• Clarified counter definitions (11.0, “Hardware Statistics Counters“ on page 53)
• Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]
• Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and
this bit was mistakenly left in the register definition.
April 2006
• Added Pb-free order code (ZL50411GDG2)
• Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 44)
since it wasn’t really discussed in the DS
• Clarified registers UCC, MCC & MCCTH
• Renamed register UCC (now PCC), as name was misleading
• Updated timing to CPU RvMII, as min. output delay should have been 0ns
5
Zarlink Semiconductor Inc.


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