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SC68C652B PDF даташит

Спецификация SC68C652B изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «5 Mbit/s (max.) with 32-byte FIFOs».

Детали детали

Номер произв SC68C652B
Описание 5 Mbit/s (max.) with 32-byte FIFOs
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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SC68C652B Даташит, Описание, Даташиты
SC68C652B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte
FIFOs, IrDA encoder/decoder, and Motorola µP interface
Rev. 01 — 25 April 2005
Product data sheet
1. General description
The SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC68C652B is pin compatible with the SC68C2550B. The SC68C652B provides
enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode data
transfer, and infrared (IrDA) encoder/decoder. The DMA mode data transfer is controlled
by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers
provide the user with error indications and operational status. System interrupts and
modem control features may be tailored by software to meet specific user requirements.
An internal loop-back capability allows on-board diagnostics. Independent programmable
baud rate generators are provided to select transmit and receive baud rates.
The SC68C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in the plastic LQFP48 package.
2. Features
s 2 channel UART with Motorola® µP interface
s 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs
s Industrial temperature range (40 °C to +85 °C)
s Software compatible with industry standard 16C450, 16C550, and SC16C650
s Up to 5 Mbit/s baud rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s 32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s Independent transmit and receive UART control
s Four selectable receive and transmit FIFO interrupt trigger levels
s Automatic software (Xon/Xoff) and hardware (RTS/CTS) flow control
s Programmable Xon/Xoff characters
s Software selectable baud rate generator
s Standard modem interface or infrared IrDA encoder/decoder interface
s Supports IrDA version 1.0 (up to 115.2 kbit/s)
s Sleep mode
s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
s Transmit, Receive, Line Status, and Data Set interrupts independently controlled









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SC68C652B Даташит, Описание, Даташиты
Philips Semiconductors
SC68C652B
www.DataSheet4U.com
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
s Fully programmable character formatting:
x 5, 6, 7, or 8-bit characters
x Even, odd, or no parity formats
x 1, 112, or 2 stop bit generation
x Baud generation (DC to 5 Mbit/s)
s False start bit detection
s Complete status reporting capabilities
s 3-state output TTL drive capabilities for bi-directional data bus and control bus
s Line break generation and detection
s Internal diagnostic capabilities:
x Loop-back controls for communications link fault isolation
s Prioritized interrupt system controls
s Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)
3. Ordering information
Table 1: Ordering information
Type number
Package
Name
Description
SC68C652BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
Version
SOT313-2
9397 750 14657
Product data sheet
Rev. 01 — 25 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 41









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SC68C652B Даташит, Описание, Даташиты
Philips Semiconductors
4. Block diagram
SC68C652B
D0 to D7
R/W
RESET
DATA BUS
AND
CONTROL
LOGIC
A0 to A3
CS
REGISTER
SELECT
LOGIC
IRQ
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
Fig 1. Block diagram of SC68C652B
SC68C652B
www.DataSheet4U.com
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
TRANSMIT
FIFO
REGISTER
FLOW
CONTROL
LOGIC
RECEIVE
FIFO
REGISTER
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TXA, TXB
IR
ENCODER
RECEIVE
SHIFT
REGISTER
RXA, RXB
IR
DECODER
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
XTAL1 XTAL2
002aab323
9397 750 14657
Product data sheet
Rev. 01 — 25 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
3 of 41










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