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PDF SC68C2550B Data sheet ( Hoja de datos )
| Número de pieza | SC68C2550B | |
| Descripción | 3.3 V and 2.5 V dual UART | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC68C2550B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs and Motorola µP interface
Rev. 02 — 28 April 2005
Product data sheet
1. General description
The SC68C2550B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC68C2550B provides enhanced UART functions with 16-byte FIFOs, modem
control interface, DMA mode data transfer. The DMA mode data transfer is controlled by
the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers
provide the user with error indications and operational status. System interrupts and
modem control features may be tailored by software to meet specific user requirements.
An internal loop-back capability allows on-board diagnostics. Independent programmable
baud rate generators are provided to select transmit and receive baud rates.
The SC68C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in a plastic LQFP48 package.
2. Features
s 2 channel UART with Motorola µP interface
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range
s Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s 16-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s Independent transmit and receive UART control
s Four selectable Receive FIFO interrupt trigger levels
s Software selectable baud rate generator
s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
s Transmit, Receive, Line Status, and Data Set interrupts independently controlled
s Fully programmable character formatting:
x 5, 6, 7, or 8-bit characters
x Even, odd, or no-parity formats
x 1, 11⁄2, or 2-stop bit
x Baud generation (DC to 5 Mbit/s)
s False start-bit detection
s Complete status reporting capabilities
s 3-state output TTL drive capabilities for bi-directional data bus and control bus
1 page  
Philips Semiconductors
SC68C2550B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 2: Pin description …continued
Symbol Pin
Type Description
R/W 15
I A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an external
CPU to an internal register that is defined by address bits A[0:2]. A logic HIGH on this pin
will load the contents of an internal register defined by address bits A[0:2] on the
SC68C2550B data bus (D[0:7]) for access by an external CPU.
OP2A,
OP2B
32, 9
O Output 2 (user-defined). This function is associated with individual channels A and B.
The state of these pins is defined by the user through the software settings of MCR[3].
OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when
MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
RESET 36
I Reset (active LOW). A logic 0 on this pin will reset the internal registers and all the
outputs. The UART transmitter output and the receiver input will be disabled during reset
time. (See Section 7.10 “SC68C2550B external reset condition” for initialization details.)
RXRDYA, 31, 18 O Receive Ready A, B (active LOW). This function is associated with PLCC44 and
RXRDYB
LQFP48 packages only. This function provides the RX FIFO/RHR status for individual
receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1
transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to
read/upload, that is, receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be used for single mode transfers
(DMA mode 0).
TXRDYA, 43, 6
TXRDYB
O Transmit Ready A, B (active LOW). This function is associated with PLCC44 and
LQFP48 packages only. These outputs provide the TX FIFO/THR status for individual
transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA mode 1
transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer
ready status is indicated by logic 0, that is, at lease one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty
locations in the FIFO or THR. This signal can also be used for single mode transfers
(DMA mode 0).
VCC
XTAL1
19, 42
13
I
I
Power supply input
Crystal or external clock input. Functions as a crystal input or as an external clock
input. A crystal can be connected between this pin and XTAL2 to form an internal
oscillator circuit. Alternatively, an external clock can be connected to this pin to provide
custom data rates. (See Section 6.5 “Programmable baud rate generator”.) See Figure 3.
XTAL2 14
O Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator
output or buffered clock output. Should be left open if an external clock is connected to
XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 kΩ
resistor.
CDA,
CDB
40, 16
I
Carrier Detect (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by
the modem for that channel.
CTSA,
CTSB
38, 23
I
Clear to Send (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready
to accept transmit data from the SC68C2550B. Status can be tested by reading MSR[4].
This pin has no effect on the UART’s transmit or receive operation.
DSRA,
DSRB
39, 20
I
Data Set Ready (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
9397 750 14941
Product data sheet
Rev. 02 — 28 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 35
5 Page 
Philips Semiconductors
SC68C2550B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.7 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the Loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally
(see Figure 4). MCR[3:0] register bits are used for controlling loop-back diagnostic testing.
In the Loop-back mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and
MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the
user data bus interface, D0 to D7. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-back connection. The receive UART
converts the serial data back into parallel data that is then made available at the user data
interface D0 to D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
9397 750 14941
Product data sheet
Rev. 02 — 28 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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