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PDF S3C2400 Data sheet ( Hoja de datos )
| Número de pieza | S3C2400 | |
| Descripción | RISC MICROPROCESSOR | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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S3C2400 RISC MICROPROCESSOR
www.DataSheet4U.com
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
INTRODUCTION
SAMSUNG's S3C2400 16/32-bit RISC microprocessor is designed to provide a cost-effective, low power, small die
size and high performance micro-controller solution for hand-held devices and general applications. To reduce total
system cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handle
virtual memory management, LCD controller (STN & TFT), 2-channel UART with handshake, 4-channel DMA,
System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, I/O Ports, RTC, 8-
channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, USB Host, USB Device, Multi-Media Card Interface, SPI
and PLL for clock generation.
The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its
low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive
applications. Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture)
An outstanding feature of the S3C2400 is its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced
RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate
16KB instruction and 16KB data caches, each with a 8-word line length.
By providing complete set of common system peripherals, the S3C2400 minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in this
document include:
• 1.8V internal, 3.3V external (I/O boundary) microprocessor with 16KB I-Cache, 16KB D-Cache, and MMU.
• External memory controller. (EDO/SDRAM Control, Chip Select logic)
• LCD controller (up to 4K color STN and 64K color TFT) with 1-ch LCD-dedicated DMA.
• 4-ch DMAs with external request pins
• 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch SPI
• 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
• MMC interface (ver 2.11)
• 2-port USB Host /1- port USB Device (ver 1.1)
• 4-ch PWM timers & 1-ch internal timer
• Watch Dog Timer
• 90-bit general purpose I/O ports/8-ch external interrupt source
• Power control: Normal, Slow, Idle, Stop and SL_IDLE mode
• 8-ch 10-bit ADC.
• RTC with calendar function.
• On-chip clock generator with PLL
1-1
1 page  
S3C2400 RISC MICROPROCESSOR
www.DataSheet4U.com
PRODUCT OVERVIEW
BLOCK DIAGRAM
ARM920T
IPA[31:0]
Instruction
MMU
IV 2A[31:0]
C13
InstructionCA
CHE
(16KB)
ID[31:0]
JTAG
ARM9TDMI
Processor core
(Internal Embedded ICE)
CP15
DD[31:0]
DV 2A[31:0]
Data
MMU
DVA[31:0]
C13
DPA[31:0]
Data
CACHE
(16KB)
External
Coproc
Interface
Write
Buffer
AMBA
Bus
I/F
WriteBack
PA Tag
RAM
WBPA[31:0]
LCD
CONT.
LCD
DMA
USB Host CONT.
ExtMaster
Clock Generator
(MPLL)
A
H
B
B
U
S
Bridge & DMA(4Ch)
BUS CONT.
Arbitor/Decode
Interrupt CONT.
Power
Management
Memory CONT.
SRAM/ROM/DRAM/SDRAM
UART 0, 1
I2C
USB Device
MMC
Watchdog
Timer
BUS CONT.
Arbitor/Decode
SPI
I2S
A
P
B
GPIO
B
U
RTC
S
ADC
Timer/PWM
0 ~ 3, 4(Internal)
Figure 1-1. S3C2400 Block Diagram
1-5
5 Page 
S3C2400 RISC MICROPROCESSOR
www.DataSheet4U.com
PRODUCT OVERVIEW
Table 1-1. 208-Pin LQFP Pin Assignment (Continued)
Pin
Number
Pin
Name
66 VD4/GPC4
67 VD5/GPC5
68 VD6/GPC6
69 VD7/GPC7
70 VD8/GPC8
71 VD9/GPC9
72 VD10/GPC10
73 VSSi
74 VDDi
75 VD11/GPC11
76 VD12/GPC12
77 VD13/GPC13
78 VDDIO
79 VSSIO
80 VD14/GPC14
81 VD15/GPC15
82 DP1/PDP0
83 DN1/PDN0
84 DP0
85 DN0
86 VSSi
87 VDDi
88 nCTS0/GPF5/nXBREQ
89 nRTS0/GPF4/nXBACK
90 TXD0/GPF2
91 RXD0/GPF0
92 TXD1/GPF3/IICSCL
93 RXD1/GPF1/IICSDA
94 OM3
95 OM2
96 OM1
97 OM0
98 VSSIO
99 VSSA_ADC
Default
Function
GPC4
GPC5
GPC6
GPC7
GPC8
GPC9
GPC10
VSSi
VDDi
GPC11
GPC12
GPC13
VDDIO
VSSIO
GPC14
GPC15
PDP0
PDN0
DP0
DN0
VSSi
VDDi
GPF5
GPF4
GPF2
GPF0
GPF3
GPF1
OM3
OM2
OM1
OM0
VSSIO
VSSA_ADC
I/O State
@BUS REQ.
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–
–
–/–
–/–
–/–
–
–
–/–
–/–
–/–
–/–
–
–
–
–
–/–/–
–/–/–
–/–
–/–
–/–/–
–/–/–
–
–
–
–
–
–
I/O State
@STOP
–/–
–/–
–/–
–/–
–/–
–/–
–/–
–
–
–/–
–/–
–/–
–
–
–/–
–/–
–/–
–/–
–
–
–
–
–/–/–
–/–/–
–/–
–/–
–/–/–
–/–/–
–
–
–
–
–
–
I/O State
@nRESET
I/O
Type
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
P vss3i
P vdd1ih_core
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
P vdd3op
P vss3op
I phbsu50ct8sm
I phbsu50ct8sm
AI pbusb
AI pbusb
AI pbusb
AI pbusb
P vss3i
P vdd1ih_core
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50ct8sm
I phbsu50cdct8sm
I phbsu50cdct8sm
I phic
I phic
I phic
I phic
P vss3op
P vss3t_abb
1-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S3C2400.PDF ] | |
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