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PDF S3C2416 Data sheet ( Hoja de datos )
| Número de pieza | S3C2416 | |
| Descripción | (S3C24xx) RISC Microprocessor | |
| Fabricantes | Samsung Electronics | |
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S3C2450/51/16
Routing Guide
S3C2450/51/16
RISC Microprocessor
August 26, 2008
REV 0.00
Confidential Proprietary of Samsung Electronics Co., Ltd
Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved
1 page  
S3C2450/51/16_ROUTING_GUIDE_ REV 0.00
www.DataSheet4U.com
1. LAND SIZE
It is of great importance to properly design the PCB land pad of FBGA package in terms of productivity of mass-
produced board. It is better to match the size of PCB land pad with that of FBGA package. There are two methods
for forming the land in PCB.
Land size is made smaller than the solder mask to form the land. The Land size is determined according to
etching time generated in the course of producing PCB. This method is a little better for routing because of small
area of copperplate, compared to the SMD method.
Outermost pads Design
Inner pads Design
S3C2450 Land Size
S3C2451 & S3C2416 Land Size
Note:
Values on this material are just recommended values and can be changed from PCB manufacture and assembly
capability.
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S3C2450/51/16_ROUTING_GUIDE_ REV 0.00
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6. SIGNAL ROUTING
6.1. USB Signal
This document conducts a guide to integrate a discrete high speed USB device onto a four layer PCB. The board
design guidelines handle trace separation, termination placement requirements and overall trace length
guidelines.
When an engineer lays out a new design, the excellent signal quality and minimized EMI problem must be
required. That is based on four layer board. The first layer is for signal layer. The second layer is for ground. The
third layer is for power and the fourth layer is for signal layer again. We should basically consider the following
instruction.
¾ HS signals should be placed on top shown in the below figure.
¾ HS clock and HS USB different pairs should be first routed with minimum trace length.
¾ Route high-speed USB signals not using Vias and stubs with using two 45 degree turns or an arc instead
of making a single 90 degree turn. This reduces signal reflections and impedance changes that affect
signal quality.
¾ Do not route USB traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use
and/or duplicate clocks.
¾ Route all traces over continuous planes (VCC and GND), with no interruptions. Avoid crossing over anti-
etch if at all possible.
¾ Their parallelism between USB differential signals with the trace spacing should be maintained. The
deviation should be minimized.
¾ The minimized length of high speed clock and periodic signal traces is highly recommended. The
suggested spacing to clock signal is 50mils ( 1mils = 0.0254mm)
¾ To prevent crosstalk, you should 20-mil minimum spacing between HS USB signal pairs. For example,
¾ Max trace length mismatch between HS USB signal pairs such as DM and DP should be under 150mils.
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet S3C2416.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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| S3C2410X | 32-Bit RISC Microprocessor | Samsung semiconductor |
| S3C2413X | 32-BIT RISC MICROPROCESSOR |  Samsung |
| S3C2416 | (S3C24xx) RISC Microprocessor | Samsung Electronics |
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