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PDF CAT24AA01 Data sheet ( Hoja de datos )
| Número de pieza | CAT24AA01 | |
| Descripción | 1-Kb and 2-Kb I2C CMOS Serial EEPROM | |
| Fabricantes | ON Semiconductor | |
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CAT24AA01, CAT24AA02
1-Kb and 2-Kb I2C CMOS
Serial EEPROM
Description
The CAT24AA01/24AA02 are 1−Kb and 2−Kb CMOS Serial
EEPROM devices internally organized as 128x8/256x8 bits.
They feature a 16−byte page write buffer and support the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocols.
In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02
have no external address pins, and are therefore suitable in
applications that require a single CAT24AA01/02 on the I2C bus.
Features
• Supports Standard, Fast and Fast−Plus I2C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial Temperature Range
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
www.onsemi.com
TSOT−23
TD SUFFIX
CASE 419AE
PIN CONFIGURATIONS
TSOT−23
SCL
VSS
SDA
15
2
34
WP
VCC
(Top View)
MARKING DIAGRAM
SCL
CAT24AA01
CAT24AA02
WP
SDA
VSS
Figure 1. Functional Symbol
RSYM
RS = Device Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
PIN FUNCTION
Pin Name
Function
SDA
Serial Data/Address
SCL Clock Input
WP Write Protect
VCC Power Supply
VSS Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 5
1
Publication Order Number:
CAT24AA01/D
1 page  
SCL FROM
MASTER
CAT24AA01, CAT24AA02
BUS RELEASE DELAY (TRANSMITTER)
18
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ tSU:DAT)
SCL
tSU:STA
SDA IN
tF tHIGH
tLOW
tLOW
tHD:STA
tHD:DAT
tR
tSU:DAT
SDA OUT
tAA tDH
Figure 5. Bus Timing
tSU:STO
tBUF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 5). The STOP
starts the internal Write cycle, and while this operation is in
progress (tWR), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 6).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 7). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 8). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh.
www.onsemi.com
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT24AA01.PDF ] | |
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