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PDF CAT24AA08 Data sheet ( Hoja de datos )
| Número de pieza | CAT24AA08 | |
| Descripción | 4-Kb and 8-Kb I2C CMOS Serial EEPROM | |
| Fabricantes | ON Semiconductor | |
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CAT24AA04, CAT24AA08
4-Kb and 8-Kb I2C CMOS
Serial EEPROM
Description
The CAT24AA04/24AA08 are 4−Kb and 8−Kb CMOS Serial
EEPROM devices internally organized as 512x8/1024x8 bits.
They feature a 16−byte page write buffer and support 100 kHz,
400 kHz and 1 MHz I2C protocols.
In contrast to the CAT24C04/24C08, the CAT24AA04/24AA08
have no external address pins, and are therefore suitable in
applications that require a single CAT24AA04/08 on the I2C bus.
Features
• Standard and Fast I2C Protocol Compatible
• Supports 1 MHz Clock Frequency
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial Temperature Range
• TSOT−23 5−lead and SOIC 8−lead Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SCL
CAT24AA04
CAT24AA08
WP
SDA
VSS
Figure 1. Functional Symbol
www.DataSheet4U.com
http://onsemi.com
SOIC−8
W SUFFIX
CASE 751BD
TSOT−23
TB SUFFIX
CASE 419AE
PIN CONFIGURATIONS
SOIC
NC 1 8 VCC
NC 2 7 WP
NC 3 6 SCL
VSS 4 5 SDA
(Top View)
SCL
VSS
SDA
TSOT−23
15
2
34
(Top View)
WP
VCC
Pin Name
SDA
SCL
WP
VCC
VSS
NC
PIN FUNCTION
Function
Serial Data/Address
Clock Input
Write Protect
Power Supply
Ground
No Connect
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
1 Publication Order Number:
CAT24AA04/D
1 page  
SCL FROM
MASTER
CAT24AA04, CAT24AA08
BUS RELEASE DELAY (TRANSMITTER)
18
9
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BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ tSU:DAT)
SCL
tSU:STA
SDA IN
tF tHIGH
tLOW
tLOW
tHD:STA
tHD:DAT
tR
tSU:DAT
SDA OUT
tAA tDH
Figure 5. Bus Timing
tSU:STO
tBUF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 6). The STOP
starts the internal Write cycle, and while this operation is in
progress (tWR), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24AA04/08 initiates the internal write
cycle. The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24AA04/08 is still
busy with the write operation, NoACK will be returned. If
the CAT24AA04/08 device has completed the internal write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24AA04/08 is shipped erased, i.e., all bytes are FFh.
http://onsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT24AA08.PDF ] | |
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