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PDF CAT34C02 Data sheet ( Hoja de datos )
| Número de pieza | CAT34C02 | |
| Descripción | 2 kb I2C EEPROM | |
| Fabricantes | ON Semiconductor | |
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CAT34C02
2 kb I2C EEPROM for DDR2
DIMM Serial Presence
Detect
Description
The CAT34C02 is a 2 kb Serial CMOS EEPROM, internally
organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits
each.
It features a 16−byte page write buffer and supports both the
Standard (100 kHz) as well as Fast (400 kHz) I2C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory) or by setting an internal Write Protect flag
via Software command (this protects the lower half of the memory).
In addition to Permanent Software Write Protection, the
CAT34C02 also features JEDEC compatible Reversible Software
Write Protection for DDR2 Serial Presence Detect (SPD)
applications operating over the 1.7 V to 3.6 V supply voltage range.
The CAT34C02 is fully backwards compatible with earlier
DDR1 SPD applications operating over the 1.7 V to 5.5 V supply
voltage range.
Features
• Supports Standard and Fast I2C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Software Write Protection for Lower 128 Bytes
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial Temperature Range
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
VCC
SCL
A2, A1, A0
WP
CAT34C02
SDA
VSS
Figure 1. Functional Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
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TSSOP−8
Y SUFFIX
CASE 948AL
TDFN−8
VP2 SUFFIX
CASE 511AK
UDFN−8
HU3 SUFFIX
CASE 517AX
UDFN−8 EP
HU4 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A0 1
VCC
A1 WP
A2 SCL
VSS SDA
TSSOP (Y), TDFN (VP2),
UDFN (HU3), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
Pin Name
A0, A1, A2
SDA
SCL
WP
VCC
VSS
PIN FUNCTION
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 14
1
Publication Order Number:
CAT34C02/D
1 page  
CAT34C02
1 0 1 0 A2 A1 A0 R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
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SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
18
BUS RELEASE DELAY
(RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ tSU:DAT)
tF tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
SDA IN
tHD:STA
tHD:DAT
tSU:DAT
SDA OUT
tAA tDH
tSU:STO
tBUF
Figure 5. Bus Timing
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 6). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
The CAT34C02 contains 256 bytes of data, arranged in 16
pages of 16 bytes each. A page is selected by the 4 most
significant bits of the address byte following the Slave
address, while the 4 least significant bits point to the byte
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 8).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34C02 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAT34C02 will not acknowledge the Slave address,
as long as internal Write is in progress.
Delivery State
The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP
flag is set. The entire 2 kb memory is erased, i.e. all bytes are
FFh.
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5
5 Page 
CAT34C02
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
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D A eb
E E2
PIN#1
IDENTIFICATION
PIN#1 INDEX AREA
A1
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
A 0.70 0.75
A1 0.00 0.02
A2 0.45 0.55
A3 0.20 REF
b 0.20 0.25
D 1.90 2.00
D2 1.30 1.40
E 2.90 3.00
E2 1.20 1.30
e 0.50 TYP
L 0.20 0.30
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
MAX
0.80
0.05
0.65
0.30
2.10
1.50
3.10
1.40
0.40
A2
D2
BOTTOM VIEW
L
FRONT VIEW
A3
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