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PDF CAT25640 Data sheet ( Hoja de datos )

Número de pieza CAT25640
Descripción 64-Kb SPI Serial CMOS EEPROM
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CAT25640
64-Kb SPI Serial CMOS
EEPROM
Description
The CAT25640 is a 64Kb Serial CMOS EEPROM device
internally organized as 8Kx8 bits. This features a 64byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAT25640 device. The device features
software and hardware write protection, including partial as well as
full array protection.
Features
20 MHz (5 V) SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
64byte Page Write Buffer
Selftimed Write Cycle
Hardware and Software Protection
Block Write Protection
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
PDIP, SOIC, TSSOP 8lead, TDFN and UDFN 8pad Packages
This Device is PbFree, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25640
SO
VSS
Figure 1. Functional Symbol
http://onsemi.com
SOIC8
V SUFFIX
CASE 751BD
UDFN8*
HU3 SUFFIX
CASE 517AX
TDFN8*
VP2 SUFFIX
CASE 511AK
PDIP8
L SUFFIX
CASE 646AA
UDFN8
HU4 SUFFIX
CASE 517AZ
TSSOP8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
PDIP (L), SOIC (V), TSSOP (Y),
TDFN* (VP2), UDFN* (HU3), UDFN (HU4)
* Not recommended for new designs
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
May, 2012 Rev. 10
1
Publication Order Number:
CAT25640/D

1 page




CAT25640 pdf
CAT25640
Table 7. A.C. CHARACTERISTICS – NEW PRODUCT (Rev F) (VCC = 1.8 V to 5.5 V, TA = 40°C to +85°C (Industrial) and
VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specified.) (Note 9)
VCC = 1.8 V 5.5 V
405C to +855C
VCC = 2.5 V 5.5 V
405C to +1255C
VCC = 4.5 V 5.5 V
405C to +855C
Symbol
Parameter
Min Max Min Max Min
fSCK
Clock Frequency
DC 5 DC 10 DC
tSU Data Setup Time
20
10
5
tH Data Hold Time
20 10
5
tWH SCK High Time
75 40 20
tWL SCK Low Time
75 40 20
tLZ HOLD to Output Low Z
50 25
tRI (Note 10)
Input Rise Time
22
tFI (Note 10)
Input Fall Time
22
tHD HOLD Setup Time
0
0
0
tCD HOLD Hold Time
10
10
5
tV Output Valid from Clock Low
70 35
tHO Output Hold Time
0
0
0
tDIS Output Disable Time
50 20
tHZ HOLD to Output High Z
100 25
tCS CS High Time
80 40 20
tCSS
CS Setup Time
30 30 15
tCSH
CS Hold Time
30 30 20
tCNS
CS Inactive Setup Time
20
20
15
tCNH
CS Inactive Hold Time
20
20
15
tWPS
WP Setup Time
10 10
10
tWPH
WP Hold Time
10 10 10
tWC (Note 11) Write Cycle Time
55
9. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Max Units
20 MHz
ns
ns
ns
ns
25 ns
2 ms
2 ms
ns
ns
20 ns
ns
20 ns
25 ns
ns
ns
ns
ns
ns
ns
ns
5 ms
Table 8. POWERUP TIMING (Notes 10, 12)
Symbol
Parameter
Max Units
tPUR
Powerup to Read Operation
1
tPUW
Powerup to Write Operation
1
12. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
ms
ms
http://onsemi.com
5

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CAT25640 arduino
CAT25640
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16bit address (see Table 13 for the number
of significant address bits).
After receiving the last address bit, the CAT25640 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25640 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the contents of the status register.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
OPCODE
BYTE ADDRESS*
SI 0 0 0 0 0 0 1 1 AN
A0
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 13)
Figure 9. READ Timing
DATA OUT
765432 10
MSB
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
OPCODE
SI
0 0000
1 01
SO HIGH IMPEDANCE
DATA OUT
7 6 5 4 3 2 10
Dashed Line = mode (1, 1)
MSB
Figure 10. RDSR Timing
http://onsemi.com
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