73S8010R PDF даташит
Спецификация 73S8010R изготовлена «Teridian Semiconductor» и имеет функцию, называемую «Low Cost Smart Card Interface». |
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Детали детали
Номер произв | 73S8010R |
Описание | Low Cost Smart Card Interface |
Производители | Teridian Semiconductor |
логотип |
25 Pages
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Simplifying System Integration™
DS_8010R_022
www.DataSheet4U.com
73S8010R
Low Cost Smart Card Interface
DATA SHEET
August 2009
DESCRIPTION
The Teridian 73S8010R is a single smart card
interface IC that provides full electrical compliance
with ISO-7816-3 and EMV 4.0 (EMV2000)
specifications.
Interfacing with the host is done through the two-wire
I2C bus and one interrupt output to inform the
system controller of the card presence and faults.
The card clock signal can be generated by an
on-chip oscillator using an external crystal, or by
connection to a clock signal.
The Teridian 73S8010R incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level-shifters drive the card signals with
the selected card voltage (3 V or 5 V), coming from an
internal Low Drop-Out (LDO) voltage regulator. This
LDO regulator is powered by a dedicated power
supply input, VPC. Digital circuitry is separately
powered by a digital power supply, VDD.
With its embedded LDO regulator, the Teridian
73S8010R is a cost-effective solution for any
application where a 5 V (typically -5% +10%) power
supply is available. Hardware support for auxiliary
I/O lines, C4 / C8 contacts is provided.
Emergency card deactivation is initiated upon
card extraction or upon any fault generated by
the protection circuitry. The fault can be a card
over-current, a VDD (digital power supply), a VPC
(regulator power supply), a VCC (card power supply)
or an over-heating fault.
The card over-current circuitry is a true current detect
function, as opposed to VCC voltage drop detection, as
usually implemented in ICC interface ICs.
The VDD voltage fault has a threshold voltage that
can be adjusted with an external resistor or resistor
network. It allows automated card deactivation at a
customized VDD voltage threshold value. It can be
used, for instance, to match the system controller
operating voltage range.
APPLICATIONS
• Set-Top-Box Conditional Access and
Pay-per-View
• Point of Sales & Transaction Terminals
• Control Access & Identification
• Multiple card and SAM reader configurations
ADVANTAGES
• Single smart card interface
• IC firmware compatible with TDA8020
• Traditional step-up converter is replaced by
an LDO regulator
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90 mA supplied to
the card)
• Small format (5x5x0.8 mm) QFN32 package option
• True card over-current detection
FEATURES
• Card Interface
• Complies with ISO-7816-3 and EMV 4.0
• An LDO voltage regulator provides 3 V / 5 V to
the card from an external power supply input
• ISO-7816-3 Activation / Deactivation
sequencer with emergency automated
deactivation on card removal or fault
detected by the protection circuitry
• Protection includes 3 voltage supervisors
that detect voltage drops on VCC card and
on power supplies VDD and VPC
• Over-current detection 150 mA max
• 1 card detection input
• Auxiliary I/O lines, for C4 / C8 contact
signals
• Host Interface
• Fast mode, 400 kbps I2C slave bus
• 8 possible devices in parallel
• One control register and one status
register
• Interrupt output to the host for fault
detection
• Crystal oscillator or host clock, up to 27 MHz
• 6 kV ESD protection on the card interface
• SO28 or QFN32 package
Rev. 1.6
© 2009 Teridian Semiconductor Corporation
1
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73S8010R Data Sheet
FUNCTIONAL DIAGRAM
DSw_w8w0.1D0atRaS_he0e2t42U.com
[4, 5, 6, 9,
16, 25, 32]
7, 8, 9
NC
[21] 22
GND
[18] 19
SCL
[19] 20
SDA
[29] 1
SAD0
[30] 2
SAD1
[31] 3
SAD2
[22] 23
INT
[23] 24
XTALIN
[24] 25
XTALOUT
VDD
[20] 21
VDDF_ADJ
[17] 18
GND
[2] 5
VPC
[3] 6
VPC FAULT
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
VDD FAULT
VCC FAULT
Int_Clk
R-C
OSC.
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
I2C
DIGITAL
&
FAULT LOGIC
ICC RESET
BUFFER
ISO-7816
SEQUENCER
ICC CLOCK
BUFFER
XTAL
OSC
CLOCK
GENERATION
OVER
TEMP
TEMP FAULT
[1] 4
GND
[12] 14
GND
[15] 17
VCC
[14] 16
RST
[13] 15
CLK
[7] 10
PRES
[26] 26
IOUC
[27] 27
AUX1UC
[28] 28
AUX2UC
ICC I/O BUFFERS
[8] 11
I/O
[11] 13
AUX1
[10] 12
AUX2
Pin numbers reference the SO28 package
[Pin numbers] reference the QFN32 Package
Figure 1: 73S8010R Block Diagram
Rev. 1.6
2
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DS_8010R_022
73S8010RwwDwa.DtaataSShheeete4Ut .com
Table of Contents
1 Pinout............................................................................................................................................. 5
2 Electrical Specifications................................................................................................................ 8
2.1 Absolute Maximum Ratings..................................................................................................... 8
2.2 Recommended Operating Conditions...................................................................................... 8
2.3 Smart Card Interface Requirements ........................................................................................ 9
2.4 Digital Signals Characteristics ............................................................................................... 11
2.5 DC Characteristics ................................................................................................................ 11
2.6 I2C Interface Characteristics .................................................................................................. 12
2.7 Voltage / Temperature Fault Detection Circuits...................................................................... 12
3 Applications Information............................................................................................................. 13
3.1 Example 73S8010R Schematics ........................................................................................... 13
3.2 System Controller Interface (I2C Bus) .................................................................................... 14
3.3 Power Supply and Voltage Supervision ................................................................................. 17
3.4 Card Power Supply ............................................................................................................... 18
3.5 Over-temperature Monitor ..................................................................................................... 18
3.6 On-chip Oscillator and Card Clock......................................................................................... 18
3.7 Activation Sequence ............................................................................................................. 19
3.8 Deactivation Sequence ......................................................................................................... 19
3.9 Interrupt ................................................................................................................................ 20
3.10 Warm Reset.......................................................................................................................... 21
3.11 I/O Circuitry and Timing......................................................................................................... 21
4 Mechanical Drawings .................................................................................................................. 22
4.1 32-pin QFN ........................................................................................................................... 22
4.2 28-Pin SO ............................................................................................................................. 23
5 Ordering Information................................................................................................................... 24
6 Related Documentation............................................................................................................... 24
7 Contact Information..................................................................................................................... 24
Revision History .................................................................................................................................. 25
Rev. 1.6
3
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