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PDF NB7L14 Data sheet ( Hoja de datos )
| Número de pieza | NB7L14 | |
| Descripción | 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB7L14
www.DataSheet4U.com
2.5V / 3.3V 7GHz/10Gbps
Differential 1:4 LVPECL
Fanout Buffer
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L14 is a differential 1:4 LVPECL fanout buffer. The
NB7L14 produces four identical LVPECL output copies of Clock or
Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the
NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock or Data distribution applications.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT Pin. This feature allows the
NB7L14 to accept various logic standards, such as LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference
output can be used to rebias capacitor−coupled differential or
single−ended input signals. The 1:4 fanout design was optimized for
low output skew applications.
The NB7L14 is a member of the GigaComm™ family of high
performance clock products.
Features
• Input Data Rate > 10.7 Gb/s
• Input Clock Frequency > 7 GHz
• 165 ps Typical Propagation Delay
• 45 ps Typical Rise and Fall Times
• <15 ps max Output Skew
• <0.8 ps maximum RMS Clock Jitter
• <15 ps pp of Data Dependent Jitter
• Differential LVPECL Outputs, 720 mV peak−to−peak, typical
• LVPECL Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
• NECL Operating Range: VCC = 0 V with GND = −2.375 V to −3.6 V
• Internal Input Termination Resistors, 50 W
• VREFAC Reference Output
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
ÇÇÇÇ1
NB7L
14
ALYWG
G
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
IN
50 W
VT
50 W
IN
VREFAC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. 2
1
Publication Order Number:
NB7L14MD
1 page  
NB7L14
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C ; (Note 11)
Symbol
Characteristic
Min Typ
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Max Unit
fMAX
fDATAMAX
VOUTPP
tPLH,
tPHL
tSKEW
Maximum Input Clock Frequency; VOUT w 400 mV
Maximum Operating Data Rate; NRZ, (PRBS23)
Output Voltage Amplitude (Note 15)
(See Figure 9)
Propagation Delay IN to Q
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
fin v 5 GHz
fin ≤ 7 GHz
78
10 11
500 720
400 450
125 165 200
15
3 15
50
GHz
Gbps
mV
ps
ps
tDC Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
fin v 7 GHz
45 50 55
%
tJITTER
RMS Random Clock Jitter (Note 13)
Peak−to−Peak Data Dependent Jitter (Note 14)
fin v 7 GHz
fin v 10.7 Gb/s
ps rms
0.5
5
0.8
15
ps pk−pk
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
100
1200
mV
tr Output Rise/Fall Times @ 1.0 GHz
tf (20% − 80%)
Qx, Qx
30 45 60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing VINPP(min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge rates
40 ps (20% − 80%).
12. Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
800
Q AMP (mV)
700
600
500
400
300
0
1.0 2.0
3.0 4.0 5.0 6.0 7.0 8.0
fin, Clock Input Frequency (GHz)
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
VCC
IN
50 W
VT
50 W
IN
Figure 4. Input Structure
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NB7L14.PDF ] | |
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