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Número de pieza | NCP1218 | |
Descripción | PWM Controller | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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PWM Controller with
Adjustable Skip Level and
External Latch Input
The NCP1218 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent standby power consumption by use of
its adjustable skip mode and integrated high voltage startup FET.
Internal frequency jittering, ramp compensation, timer−based fault
detection and a latch input make this controller an excellent
candidate for converters where ruggedness and component cost are
the key constraints.
The Dynamic Self Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1218. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Due to its high voltage technology, the IC can be
directly connected to the high voltage dc rail.
Features
• Fixed−Frequency 65 kHz Current−Mode Operation with Ramp
Compensation
• Dynamic Self Supply Eliminates the Need for an Auxiliary Winding
• Timer−Based Fault Protection for Improved Overload Detection
• Cycle Skip Reduces Input Power in Standby Mode
• Latched Overload Protection
• Internal High Voltage Startup Circuit
• Accurate Current Limit Detector (±5%)
• Adjustable Skip Level
• Latch Input for Easy Implementation of Overvoltage and
Overtemperature Protection
• Frequency Modulation for Softened EMI Signature
• 500 mA/800 mA Peak Source/Sink Current Drive Capability
• Pin to Pin Compatible with the Existing NCP12XX Series
• These Devices are Pb−Free and Halogen Free/BFR Free*
Typical Applications
• AC−DC Adapters for Notebooks, LCD Monitors
• Offline Battery Chargers
• Consumer Electronic Appliances STB, DVD, DVDR
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SOIC−7
D SUFFIX
CASE 751U
MARKING DIAGRAM
8
1218AZ
ALYW
G
1
1218A= Specific Device Code
Z = Frequency= (6 = 65 kHz)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN CONNECTIONS
Skip/latch
FB
CS
GND
1
(Top View)
HV
VCC
DRV
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 1
1
Publication Order Number:
NCP1218/D
1 page NCP1218
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Table 2. MAXIMUM RATINGS (Notes 1 − 4)
Rating
Symbol
Value
Unit
HV Voltage
HV Current
Supply Voltage
Supply Current
Skip/latch Voltage
Skip/latch Current
FB Voltage
FB Current
CS Voltage
CS Current
DRV Voltage
DRV Current
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (TA = 25°C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7) (Note 4)
VHV
IHV
VCC
ICC
VSkip/latch
ISkip/latch
VFB
IFB
VCS
ICS
VDRV
IDRV
TJ
Tstg
PD
−0.3 to 500
100
−0.3 to 20
100
−0.3 to 9.5
100
−0.3 to 5.0
100
−0.3 to 5.0
100
−0.3 to 20
−500 to 800
–40 to 150
–60 to 150
0.92
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
°C
°C
W
Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7)
°C/W
Junction to Air, Low conductivity PCB (Note 3)
Junction to Lead, Low conductivity PCB (Note 3)
Junction to Air, High conductivity PCB (Note 4)
Junction to Lead, High conductivity PCB (Note 4)
RθJA
RθJL
RθJA
RθJL
177
75
136
69
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 6: Human Body Model 3000 V per JEDEC JESD22−A114−F.
Pins 1– 6: Machine Model Method 300 V per JEDEC JESD22−A115−A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains Latch−Up protection and exceeds ±100 mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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5
5 Page NCP1218
TYPICAL CHARACTERISTICS
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1.2
1.1 Rskip = 48.7 kW
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Adjustable Skip Threshold vs.
Junction Temperature
10
9
8
7
6
5
4
3
2
1
0
−50 −25
0
25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Soft−Start Period vs. Junction
Temperature
150
1.2
1.0
0.8
0.6
0.4
0.2
0
1
10
100
1000
10000
RSkip, EXTERNAL SKIP RESISTOR (kW)
Figure 22. Skip Threshold vs. Skip Resistor
420
410
400
390
380
370
360
350
340
330
320
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 24. Overload Timer Period vs. Junction
Temperature
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11
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Páginas | Total 20 Páginas | |
PDF Descargar | [ Datasheet NCP1218.PDF ] |
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