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SC16C852L PDF даташит

Спецификация SC16C852L изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «16 mode or 68 mode bus interface».

Детали детали

Номер произв SC16C852L
Описание 16 mode or 68 mode bus interface
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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SC16C852L Даташит, Описание, Даташиты
SC16C852L
1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared
(IrDA) and 16 mode or 68 mode bus interface
Rev. 03 — 18 January 2008
Product data sheet
1. General description
The SC16C852L is a 1.8 V, low power, dual channel Universal Asynchronous Receiver
and Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. The SC16C852L is pin compatible with the SC16C652B. SC16C852L
can be programmed to operate in extended mode (see Section 6.2) where additional
advanced UART features are available. The SC16C852L UART provides enhanced UART
functions with 128-byte FIFOs, modem control interface, DMA mode data transfer, and
IrDA encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger
levels and the TXRDY and RXRDY signals. On-board status registers provide the user
with error indications and operational status. System interrupts and modem control
features may be tailored by software to meet specific user requirements. An internal
loopback capability allows on-board diagnostics. Independent programmable baud rate
generators are provided to select transmit and receive baud rates.
The SC16C852L with Intel (16 mode) or Motorola (68 mode) bus host interface operates
at 1.8 V and is available in plastic LQFP48, TFBGA36 and very small (Micro-UART)
HVQFN32 packages.
2. Features
I Dual channel high performance UART
I Intel or Motorola bus interface selectable using 16/68 pin
I 1.8 V operation
I Up to 5 Mbit/s data rate
I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
I 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
I 128 programmable Receive and Transmit FIFO interrupt trigger levels
I 128 Receive and Transmit FIFO reporting levels (level counters)
I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
I Industrial temperature range (40 °C to +85 °C)
I Pin, function, and software compatible to SC16C652B in LQFP48 package
I 128 hardware and software trigger levels
I Automatic 9-bit mode (RS-485) address detection
I Automatic RS-485 driver turn-around with programmable delay
I Dual channel concurrent write
I UART software reset
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SC16C852L Даташит, Описание, Даташиты
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
I High resolution clock prescaler, from 0 to 15 with granularity of 116 to allow
non-standard UART clock to be used
I Programmable Xon/Xoff characters
I Software selectable baud rate generator
I Support IrDA version 1.0 (up to 115.2 kbit/s)
I Standard modem interface or infrared IrDA encoder/decoder interface
I Enhanced Sleep mode and low power feature
I Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
I Independent transmitter and receiver enable/disable
I Pb-free, RoHS compliant packages offered
3. Ordering information
Table 1. Ordering information
Type number Package
Name
Description
SC16C852LIB LQFP48 plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm
SC16C852LIBS HVQFN32 plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5 × 5 × 0.85 mm
SC16C852LIET TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls;
body 3.5 × 3.5 × 0.8 mm
Version
SOT313-2
SOT617-1
SOT912-1
SC16C852L_3
Product data sheet
www.DataSheet.in
Rev. 03 — 18 January 2008
© NXP B.V. 2008. All rights reserved.
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SC16C852L Даташит, Описание, Даташиты
NXP Semiconductors
4. Block diagram
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
SC16C852L
D0 to D7
IOR
IOW
RESET
DATA BUS
AND
CONTROL
LOGIC
A0 to A2
CSA
CSB
REGISTER
SELECT
LOGIC
TRANSMIT
FIFO
REGISTER
FLOW
CONTROL
LOGIC
RECEIVE
FIFO
REGISTER
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TXA, TXB
IR
ENCODER
RECEIVE
SHIFT
REGISTER
RXA, RXB
IR
DECODER
LOWPWR
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
POWER-
DOWN
CONTROL
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
Fig 1. Block diagram of SC16C852L (16 mode)
XTAL1 XTAL2
002aac403
SC16C852L_3
Product data sheet
www.DataSheet.in
Rev. 03 — 18 January 2008
© NXP B.V. 2008. All rights reserved.
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