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PDF OV5620 Data sheet ( Hoja de datos )
| Número de pieza | OV5620 | |
| Descripción | Color CMOS QSXGA (5.17 MPixel) CAMERACHIP | |
| Fabricantes | Ommivision | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de OV5620 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Omni ision
®
Advanced Information
Preliminary Datasheet
OV5620 Color CMOS QSXGA (5.17 MPixel) CAMERACHIPTM with OmniPixel2TM Technology
General Description
The OV5620 (color) CAMERACHIPTM is a high performance
5.17 mega-pixel image sensor for digital still image and
video camera products.
This device incorporates a 2592 x 1944 image array and
an on-chip 10-bit A/D converter capable of operating at up
to 7.5 frames per second (fps) in full resolution. The
OV5620 can also output 864 x 600 resolution at 60 fps
enabling enhanced video viewing on TV. Proprietary
sensor technology utilizes advanced algorithms to cancel
Fixed Pattern Noise (FPN), eliminate smearing, and
drastically reduce blooming, dark current and lens
shading. The control registers allow for flexible control of
timing, polarity, and CAMERACHIP operation, which, in turn,
allows the engineer a great deal of freedom in product
design.
Note: The OV5620 is available in a
Pb lead-free package.
Features
• Optical black level calibration
• Video or snapshot operations
• Programmable/Auto Exposure and Gain Control
• Programmable/Auto White Balance Control
• Horizontal and vertical sub-sampling for high frame
rate with excellent image quality
• High frame rate output mode
• Programmable image windowing
• Variable frame rate control
• On-chip Luminance Average Counter
• VarioPixel® (binning) 1:2, 1:3, 1:4
• Subsampling (skip) 1:2, 1:3, 1:4, 1:8
• Flash control output (strobe pin)
• 50/60 Hz light auto detection
• Image vertical flip / horizontal mirror
• Defect pixel correction
• Internal/External frame synchronization
• Serial bus interface
• Power-on reset and power-down modes
Ordering Information
Product
OV05620-C03A (Color)
Package
CLCC-48
Applications
• Digital still cameras
• Digital video cameras
• PC camera/dual mode
• Video conference equipment
Key Specifications
Power Supply
Power
Requirements
Array Size
Analog
Digital
I/O
Active
Standby
Electronics Exposure
Shutter
Output Format
Lens Size
Lens Chief Ray Angle
Input Clock
Maximum System Clock
Maximum Data Rate
Full
Max Image
Transfer Rate
1.3Mpixel
D1MD
VGA
QVGA
Sensitivity
S/N Ratio
Dynamic Range
Scan Mode
Pixel Size
Dark Current
Fixed Pattern Noise
Image Area
Package Dimensions
2592 x 1944
2.6 ~ 3.0V
1.3V + 5%
1.7 ~ 3.3V
TBD
250 µA
1 TLINE to 1/F
where F = frame rate
Electronic rolling shutter,
snapshot
10-bit digital RGB Raw data
1/2.5"
12.5°
6 - 27 MHz
48 MHz
48 MHz
7.5 fps
30 fps
60 fps
60 fps
120 fps
TBD
TBD
TBD
Progressive
2.2 µm x 2.2 µm
TBD
TBD
5.808 mm x 4.294 mm
14.22 mm x 14.22 mm
Figure 1 OV5620 Pin Diagram (Top View)
30 29 28 27 26 25 24 23 22 21 20 19
NC 31
18 NC
NC 32
17 NC
DVDD 33
16 Y3
Y4 34
15 Y2
Y5 35
Y6 36
Y7 37
Y8 38
OV5620
14 Y1
13 Y0
12 EXP_STB
11 RESET_B
Y9 39
10 FREX
PCLK 40
9 PWDN
NC 41
8 NC
NC 42
7 NC
43 44 45 46 47 48 1 2 3 4 5 6
5620CLCC_DS_001
© 2006 OmniVision Technologies, Inc.
Version 1.1, May 9, 2006
VarioPixel, OmniVision, and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc.
OmniPixel2 and CameraChip are trademarks of OmniVision Technologies, Inc.
These specifications are subject to change without notice.
www.DataSheet.in
1 page  
Omni ision
Functional Description
Frame Rate Adjust
The OV5620 offers four methods for frame rate
adjustment:
• Clock prescaler: (see “CLKRC” on page 17)
By changing the system clock divide ratio, the frame
rate and pixel rate will change together. This method
can be used for dividing the frame/pixel rate by: 1/2,
1/3, 1/4 … 1/64 of the PLL output clock.
• Horizontal blanking: (see “REG2A” on page 20 and
see “EXHCL” on page 20)
By changing the horizontal blank timing in each line
after active pixel output, the frame rate can be
changed while leaving the pixel rate as is.
• Vertical blanking:
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 20 and “ADDVSH”
on page 20) or after the active lines (see “DMLNL” on
page 21 and “DMLNH” on page 21), the frame rate
can be altered while the pixel rate remains the same.
• PLL control: Supports more flexible clock control
SCCB Interface
The OV5620 provides an on-chip SCCB serial control port
that allows access to all internal registers, for complete
control and monitoring of OV5620 operation.
Refer to OmniVision Technologies Serial Camera Control
Bus (SCCB) Specification for detailed usage of the serial
control port.
Figure 10 Slave Mode Connection
Y[9:0]
RESET_B
PWDN
XVCLK
MHSYNC
MVSYNC
MCLK
OV5620
Master
Device
5620CLCC_DS_010
Figure 11 Slave Mode Timing
VSYNC
HSYNC
TVS
Tframe
Tline
THS
MCLK
Tclk
5620CLCC_DS_011
NOTE:
1) THS > 6 Tclk, Tvs > Tline
2) Tline = 3252 x Tclk (QSXGA); Tline = 1640 x Tclk (1.3 Mpixel)
3) Tframe = 1968 x Tline (QSXGA); Tframe = 976 x Tline (1.3 Mpixel)
Channel Average Calculator
The OV5620 provides average output level data for
frame-averaged luminance level. Access to the data is
provided via the SCCB interface.
Slave Operation Mode
The OV5620 can be programmed to operate in slave
mode (default is master mode).
When used as a slave device, the OV5620 re-uses input
pins, RESET_B and PWDN, for use as horizontal and
vertical synchronization input triggers supplied by a
master device. The master device must provide the
following signals:
1. System clock MCLK to XVCLK pin
2. Horizontal sync MHSYNC to RESET_B pin
3. Vertical frame sync MVSYNC to PWDN pin
See Figure 10 for slave mode connections and Figure 11
for detailed timing considerations.
Reset_B
The OV5620 includes a RESET_B pin (pin 11) that forces
a complete hardware reset when it is pulled low (ground).
The OV5620 clears all registers and resets them to their
default values when a hardware reset occurs. A reset can
also be initiated through the SCCB interface.
Power Down Mode
Two methods are available to place the OV5620 into
power-down mode.
• Hardware power-down may be selected by pulling
the PWDN pin (pin 9) high (DOVDD). When this
occurs, the OV5620 internal device clock is halted
and all internal counters are reset. The current draw
is less than 250 µA in this standby mode.
• Software power-down through the SCCB interface
suspends internal circuit activity but does not halt the
device clock. The current requirements drop to less
than 1 mA in this mode. All register content is
maintained in standby mode.
Version 1.1, May 9, 2006
Proprietary to OmniVision Technologies, Inc.
5
www.DataSheet.in
5 Page 
Omni ision
Timing Specifications
Figure 14 Serial Bus Timing Diagram
SCL
tSU:STA
tF
t
LOW
tHD:STA
SDA IN
tHIGH
t
HD:DAT
SDA OUT
tAA
Table 7
Serial Bus Timing Specifications
Symbol
Parameter
fSCL
tLOW
tHIGH
tAA
tBUF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tR, tF
tDH
Clock Frequency
Clock Low Period
Clock High Period
SCL low to Data Out valid
Bus free time before new START
START condition Hold time
START condition Setup time
Data-in Hold time
Data-in Setup time
STOP condition Setup time
Serial Bus Rise/Fall times
Data-out Hold time
Timing Specifications
t
R
t
SU:DAT
tSU:STO
tDH
tBUF
5620CLCC_DS_014
Min Typ Max Unit
400 KHz
1.3 µs
600 ns
100 900 ns
1.3 µs
600 ns
600 ns
0 µs
100 ns
600 ns
300 ns
50 ns
Version 1.1, May 9, 2006
www.DataSheet.in
Proprietary to OmniVision Technologies, Inc.
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| PDF Descargar | [ Datasheet OV5620.PDF ] | |
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