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PDF NLX1G74 Data sheet ( Hoja de datos )
| Número de pieza | NLX1G74 | |
| Descripción | Single D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NLX1G74
Single D Flip-Flop
The NLX1G74 is a high performance, full function edge−triggered
D Flip−Flop in ultra−small footprint. The NLX1G74 input structures
provide protection when voltages up to 7.0 V are applied, regardless of
the supply voltage.
Features
• Extremely High Speed: tPD = 2.6 ns (typical) at VCC = 5.0 V
• Designed for 1.65 V to 5.5 V VCC Operation
• Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
• 24 mA Balanced Output Sink and Source Capability at VCC = 3.0 V
• Balanced Propagation Delays
• Overvoltage Tolerant (OVT) Input Pins
• Ultra Small Package
• This is a Pb−Free Device
TRUTH TABLE
Inputs
Outputs
PR CLR CP D Q Q
Operating Mode
L HX XHL
H L X X LH
L L X XHH
Asynchronous Set
Asynchronous Clear
Undetermined
HH↑ hHL
HH↑ l LH
Load and Read Register
H H ↑ X NC NC
Hold
H = High Voltage Level
h = High Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
NC = No Change
X = High or Low Voltage Level and Transitions are Acceptable
↑ = Low−to−High Transition
↑ = Not a Low−to−High Transition
For ICC reasons, DO NOT FLOAT Inputs
http://onsemi.com
18
UQFN8
MU SUFFIX
CASE 523AN
MARKING
DIAGRAM
1
AA MG
G
AA = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAM
CP D Q
7 65
VCC 8
4 GND
1 23
PR CLR Q
LOGIC DIAGRAM
PR
D
CP
CLR
1
63
Q
75
2
Q
VCC = 8, GND = 4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 0
www.DataSheet.in
1
Publication Order Number:
NLX1G74/D
1 page  
www.DataSheet.in
NLX1G74
Vcc
D 50%
ts
CP
th
50%
tw
0V
Vcc
fmax
tPLH, tPHL
0V
VOH
Q, 50%
Q VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
PR 50%
CLR
Q
tPLH
50%
50%
tPHL
50%
Q
PR, CLR
tPHL
50%
tPLH
50%
WAVEFORM 2 − PROPAGATION DELAYS
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
tw
50%
trec
CP
50%
tw
WAVEFORM 3 − RECOVERY TIME
tR = tF = 3.0 ns from 10% to 90%; f = 1 MHz; tw = 500 ns
Output Reg: VOL ≤ 0.8 V, VOH ≥ 2.0 V
Figure 1. AC Waveforms
VCC
PULSE
GENERATOR
DUT
RT
CL RL
Vcc
0V
Vcc
0V
VOL
VOH
Vcc
0V
Vcc
0V
Figure 2. Test Circuit
http://onsemi.com
5
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NLX1G74.PDF ] | |
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