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PDF HC1S80 Data sheet ( Hoja de datos )
| Número de pieza | HC1S80 | |
| Descripción | HardCopy Stratix Device Family | |
| Fabricantes | Altera Corporation | |
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Section I. HardCopy Stratix
Device Family Data Sheet
This section provides designers with the data sheet specifications for
HardCopy® Stratix structured ASICs. The chapters contain feature
definitions of the internal architecture, JTAG boundary-scan testing
information, DC operating conditions, AC timing parameters, and a
reference to power consumption for HardCopy Stratix structured ASICs.
This section contains the following:
■ Chapter 1, Introduction to HardCopy Stratix Devices
■ Chapter 2, Description, Architecture, and Features
■ Chapter 3, Boundary-Scan Support
■ Chapter 4, Operating Conditions
■ Chapter 5, Quartus II Support for HardCopy Stratix Devices
■ Chapter 6, Design Guidelines for HardCopy Stratix Performance
Improvement
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Altera Corporation
www.DataSheet.in
Section I–1
Preliminary
1 page  
Features
■ Supports high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,
double data rate (DDR) SDRAM, DDR fast-cycle RAM (FCRAM),
and single data rate (SDR) SDRAM
■ Support for multiple intellectual property (IP) megafunctions from
Altera® MegaCore® functions, and Altera Megafunction Partners
Program (AMPPSM) megafunctions
■ Available in space-saving flip-chip FineLine BGA® and wire-bond
packages (Tables 1–2 and 1–3)
■ Optional emulation of original FPGA configuration sequence
■ Optional instant-on power-up
1 The actual performance and power consumption improvements
over the Stratix equivalents mentioned in this data sheet are
design-dependent.
Table 1–2. HardCopy Stratix Device Package Options and I/O Pin Counts
Note (1)
Device
HC1S25
HC1S30
HC1S40
HC1S60
HC1S80
672-Pin
780-Pin
1,020-Pin
FineLine BGA (2) FineLine BGA (3) FineLine BGA (3)
473
597
613 (4)
782
782
Notes to Table 1–2:
(1) Quartus II I/O pin counts include one additional pin, PLLENA, which is not a
general-purpose I/O pin. PLLENA can only be used to enable the PLLs.
(2) This device uses a wire-bond package.
(3) This device uses a flip-chip package.
(4) In the Stratix EP1S40F780 FPGA, the I/O pins U12 and U18 are general-purpose
I/O pins. In the FPGA prototype,
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the HardCopy Stratix
HC1S40F780 device, U12 and U18 must be connected to ground. The
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE and HC1S40F780 pin-outs are
identical.
Altera Corporation
September 2008
www.DataSheet.in
1–3
Preliminary
5 Page 
Description, Architecture, and Features
Although memory resource implementation is equivalent, the number of
specific M-RAM blocks are not necessarily the same between
corresponding Stratix and HardCopy Stratix devices. Table 2–3 shows the
number of M-RAM blocks available in each device.
Table 2–3. HardCopy Stratix and Stratix M-RAM Block Comparison
HardCopy Stratix
Stratix
Device
HC1S25
HC1S30
HC1S40
HC1S60
HC1S830
M-RAM Blocks
2
2
2
6
6
Device
EP1S25
EP1S30
EP1S40
EP1S60
EP1S830
M-RAM Blocks
2
4
4
6
9
In HardCopy Stratix devices, it is not possible to preload RAM contents
using a MIF after powering up; the output registers of memory blocks
will have unknown values. This occurs because there is no configuration
process that is executed.
1
Violating the setup or hold time requirements on address
registers could corrupt the memory contents. This requirement
applies to both read and write operations.
Table 2–4 illustrates the differences between HardCopy Stratix and
Stratix memory.
Table 2–4. HardCopy Stratix and Stratix Memory Comparison
HardCopy Stratix
Stratix
HC1S30 and HC1S40 devices have
two M-RAM blocks. HC1S80 devices
have six M-RAM blocks.
EP1S30 and EP1S40 devices have four
M-RAM blocks. EP1S80 devices have
nine M-RAM blocks.
It is not possible to initialize M512 and
M4k RAM contents during power-up.
The contents of M512 and M4K RAM
blocks can be preloaded during
configuration with data specified in a
MIF.
The contents of memory output
registers are unknown after POR.
The contents of memory output
registers are initialized to ‘0’ after POR.
Altera Corporation
September 2008
www.DataSheet.in
2–5
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HC1S80.PDF ] | |
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