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PDF W78LE52 Data sheet ( Hoja de datos )
| Número de pieza | W78LE52 | |
| Descripción | 8-BIT MICROCONTROLLER | |
| Fabricantes | Winbond | |
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W78LE52/W78L052A
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................... 2
2. FEATURES....................................................................................................................................... 2
3. PIN CONFIGURATIONS .................................................................................................................. 3
4. PIN DESCRIPTION .......................................................................................................................... 4
5. FUNCTIONAL DESCRIPTION ......................................................................................................... 5
5.1 Eight-source interrupt information: .......................................................................................... 6
6. ON-CHIP FLASH EPROM CHARACTERISTICS .......................................................................... 10
7. SECURITY BITS............................................................................................................................. 12
8. ABSOLUTE MAXIMUM RATINGS ................................................................................................. 13
9. DC CHARACTERISTICS................................................................................................................ 14
10. AC CHARACTERISTICS................................................................................................................ 16
11. TIMING WAVEFORMS................................................................................................................... 19
12. TYPICAL APPLICATION CIRCUITS.............................................................................................. 22
13. PACKAGE DIMENSIONS............................................................................................................... 24
14. REVISION HISTORY...................................................................................................................... 26
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Publication Release Date: November 6, 2006
- 1 - Revision A6
1 page  
W78LE52/W78L052A
5. FUNCTIONAL DESCRIPTION
The W78L052 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of
the W78L052: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like
Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
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Publication Release Date: November 6, 2006
- 5 - Revision A6
5 Page 
W78LE52/W78L052A
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if VPP = VEP (14.5V), CE is high and
OE is low.
PROGRAM/ERASE INHIBIT OPERATION
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
P3.6
ERRO
OPERATIONS
P3.0
(A9
CTRL)
P3.1
(A13
CTRL)
P3.2
(A14
CTRL)
(ERRO
R!
OBJEC
TS
P3.3
CANN
OT BE
(OE CREAT
CTRL) ED
FROM
EDITIN
G
FIELD
CODE
P3.7
( OE )
R!
OBJEC
TS
CANN
OT BE
CREAT
ED
FROM
EDITIN
G
FIELD
CODE
S.
P2, P1
(A15..A0)
S.) (VPP)
P0
(D7..D0)
NOTE
Read
0 0 0 0 0 0 1 Address Data Out
Output Disable 0 0 0 0 0 1 1 X Hi-Z
Program
0 0 0 0 0 1 VCP Address Data In
Program Verify 0 0 0 0 1 0 VCP Address Data Out @3
Erase
1
0
0
0
0
1
VEP
A0: 0,
others: X
Data In
0FFH
@4
Erase Verify 1 0 0 0 1 0 VEP Address Data Out @5
Program/Erase
Inhibit
X
0
0
0
1
1
VCP/
VEP
X
X
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
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- 11 -
Publication Release Date: November 6, 2006
Revision A6
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet W78LE52.PDF ] | |
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