|
|
PDF NT7501 Data sheet ( Hoja de datos )
| Número de pieza | NT7501 | |
| Descripción | 33 X 100 RAM-Map LCD Controller/Driver | |
| Fabricantes | Novatek | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NT7501 (archivo pdf) en la parte inferior de esta página. Total 38 Páginas | ||
|
No Preview Available !
NT7501
33 X 100 RAM-Map LCD Controller/Driver
Features
! Direct RAM data display using the display RAM. When
RAM data bit is 0, it is not displayed. When RAM data bit
is 1, it is displayed. (In normal display mode)
! RAM capacity: 65 X 132 = 8580 bits
! Many command functions: Read/Write Display Data,
Display ON/OFF, Normal/Reverse Display, Page
Address Set, Set Display Start Line, Set LCD Bias,
Electronic contrast Controls, Read Modify Write, Select
Segment Driver Direction and Power Save
General Description
The NT7501 is a single-chip LCD driver for dot-matrix liquid
crystal displays, which is directly connectable to a
microcomputer bus. It accepts 8-bit serial or parallel display
data directly sent from a microcomputer and stores it in an
on-chip display RAM. It generates a LCD drive signal
independent of the microprocessor clock.
The set of the on-chip display RAM of 65 X 132 bits, and a
one-to-one correspondence between the LCD panel pixel
dots and the on-chip RAM bits, permits implementation of
displays with a high degree of freedom.
! High-speed 8-bit microprocessor interface allowing direct
connection to both the 8080 and 6800
! Serial interface
! Single supply operation, 2.4 - 3.5V
! Maximum 9V LCD driving output voltage
! 2X / 3X / 4X on chip DC-DC converter
! Voltage regulator
! Voltage follower (LCD bias: 1/5 or 1/6)
! On chip oscillator
As a total of 133 circuits of common and segment outputs
are incorporated, a single chip of NT7501 can make 33 X
100 dots displays.
No external operation clock is required for RAM read/write
operations. Accordingly, this driver can be operated with
minimum current consumption and its on-board low-current-
consumption liquid crystal power supply can implement a
high-performance handy display system with minimal current
consumption and a minute LSI configuration.
www.DataSheet.in
1 V2.0
1 page  
System Bus Connection Terminals
Pad No.
Symbol
27 - 34
D0 - D7
(SI)
(SCL)
16
8
11 - 13
18
A0
RES
CS1 CS2
RD
(E)
17 WR
(RW )
14 C86
10 P/S
7 M/S
4 CL
NT7501
I/O Description
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus.
I/O When the serial interface is selected (P/S = “L”), then D7 serves as the
serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
This is connected to the least significant bit of the normal MPU address
I
bus, and it determines whether the data bits are data or a command.
A0 = “H”: Indicate that D0 to D7 are display data.
A0 = “L”: Indicates that D0 to D7 are control data.
When RES is set to “L”, the settings are initialized.
I
The reset operation is performed by the RES signal level.
I This is the chip select signal. When CS1 = “L” and CS2 = “H”, then the
chip select becomes active and data/command I/O are enabled
When connected to an 8080 MPU, it is active LOW. This pad is
connected to the RD signal of the 8080MPU, and the NT7501 data bus
I is in an output statue when this signal is “L”.
When connected to a 6800 Series MPU, this is active HIGH. This is
used as an enable clock input of the 6800 series MPU.
When connected to an 8080 MPU, this is active LOW. This terminal
connects to the 8080 MPU WR signal . The signals on the data bus are
latched at the rising edge of the WR signal.
I When connected to a 6800 Series MPU: This is the read/write control
signal input terminal.
When R W = “H”: Read.
When R W = “L”: Write.
This is the MPU interface switch terminal.
I C86 = “H”: 6800 Series MPU interface.
C86 = “L”: 8080 Series MPU interface.
This is the parallel data input/serial data input switch terminal.
P/S = “H”: Parallel data input.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S Data/Command Data Read/Write Serial Clock
I "H" A0 D0 to D7 RD WR
"L" A0 SI (D7) Write only SCL (D6)
When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open.
RD (E) and WR ( R / W ) are fixed to either “H” or “L”. With serial data
input, RAM display data reading is not supported.
This terminal selects the master/slave operation for the NT7501 chips.
I
Master operation outputs the timing signals that are required for the
LCD display, while slave operation inputs the timing signals required for
the liquid crystal display, synchronizing the liquid crystal display system.
This is the display clock input terminal. When the NT7501 chips are
I/O used in master/slave mode, the various CL terminals must be
connected.
www.DataSheet.in
5
5 Page 
NT7501
Display Timing Generator
This section explains how the display timing generator circuit operates.
Signal Generation to Line Counter and Display Data Latch Circuit
The display clock (CL) generates a clock to the line counter and a latch signal to the display data latch circuit.
The line address of the display RAM is generated in synchronization with the display clock. 100-bit display data is latched by the
display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pad.
The display data is read to the LCD drive circuit completely independent of access to the display data RAM from the
microprocessor.
LCD AC Signal (FR) Generation
The display clock generates an LCD AC signal (FR). The FR causes the LCD drive circuit to generate a AC drive waveform.
It generates a 2-frame AC drive waveform.
When the NT7501 is operated in slave mode on the assumption of multi-chip, the FR pad and CL pad become input pads.
Common Timing Signal Generation
The display clock generates an internal common timing signal and a start signal (DYO) to the common driver. A display clock
resulting from frequency division of an oscillation clock is output from the CL pad.
When an AC signal (FR) is switched, a high pulse is output as a DYO output at the turning edge of the previous display clock.
Refer to Figure 5. The DYO output is output only in master mode.
When the NT7501 is used for multi-chip, the slave requires to receive the FR, CL, DOF signals from the master.
Table 4 shows the FR, CL, DYO and DOF status.
Table 4.
Model
Operation mode FR
CL DYO
NT7501
Master
Slave
Output
Input
Output
Input
Output
HZ
HZ denotes a high-impedance status
Example of NT7501 1/33 duty (Dual-frame AC driver waveforms)
DOF
Output
Input
32 33 1
2345
6
28 29 30 31 32 33 1 2 3 4 5
CL
FR
DYO
COM0
COM1
RAM
data
SEGn
Figure 5.
V0
V1
V4
VSS
V0
V1
V4
VSS
V0
V2
V3
VSS
www.DataSheet.in
11
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet NT7501.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NT7501 | 33 X 100 RAM-Map LCD Controller/Driver | Novatek |
| NT7502 | 65 X 132 RAM-Map LCD Controller / Driver | Novatek |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |