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GS880F36T-11.5 PDF даташит

Спецификация GS880F36T-11.5 изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «8Mb Sync Burst SRAMs».

Детали детали

Номер произв GS880F36T-11.5
Описание 8Mb Sync Burst SRAMs
Производители GSI Technology
логотип GSI Technology логотип 

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GS880F36T-11.5 Даташит, Описание, Даташиты
100 Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
GS880F18/36T-10/11/11.5/12/14
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
www.D10atnaSshe-e1t44Un.csom
3.3V VDD
3.3V & 2.5V I/O
Features
• Flow through mode operation.
• 3.3V +10%/-5% Core power supply.
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• 100-lead TQFP package
-10 -11 -11.5 -12 -14
Flow Through tKQ 10ns 11ns 11.5ns 12ns 14ns
2-1-1-1 tCycle 10ns 15ns 15ns 15ns 15ns
IDD 225mA 180mA 180mA 180mA 175mA
Functional Description
Applications
The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin option
(pin 14 on TQFP). Board sites for Flow through Burst RAMS should
be designed with VSS connected to the FT pin location to ensure the
broadest access to multiple vendor sources. Boards designed with FT
pin pads tied low may be stuffed with GSI’s Pipeline/Flow through
configurable Burst RAMS or any vendor’s Flow through or
configurable Burst SRAM. Bumps designed with the FT pin location
tied High or floating must employ a non-configurable Flow through
Burst RAM, like this RAM, to achieve Flow through functionality.
88018/32/36TByte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36T operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(VDDQ) pins are used to de-couple output noise from the internal
circuit.
Rev: 1.03 3/2000
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N









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GS880F36T-11.5 Даташит, Описание, Даташиты
GS880F18 100 Pin TQFP Pinout
Preliminary
GS880F18/36T-10/11/11.5/12/14
www.DataSheet4U.com
NC
NC
NC
VDDQ
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
NC
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
512K x 18
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A18
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 1.03 3/2000
2/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N









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GS880F36T-11.5 Даташит, Описание, Даташиты
GS880F32 100 Pin TQFP Pinout
Preliminary
GS880F18/36T-10/11/11.5/12/14
www.DataSheet4U.com
NC
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
NC
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
256K x 32
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
Rev: 1.03 3/2000
3/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N










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